addressdecoder.vhd

来自「关于对数据采集卡的基于PC104总线的读写程序」· VHDL 代码 · 共 59 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY AddressDecoder IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		IOR : IN STD_LOGIC;
		IOW : IN STD_LOGIC;
		AEN : IN STD_LOGIC;
		SA : IN STD_LOGIC_VECTOR(9 downto 0);
		SBHE : IN STD_LOGIC;
		RESET : IN STD_LOGIC;
		CS_8254 : OUT STD_LOGIC;
		CS_D : OUT STD_LOGIC;
		RD_Fifo : OUT STD_LOGIC;
		IOCS16 : OUT STD_LOGIC;
		IERegAddr : OUT STD_LOGIC;
		ISRegAddr : OUT STD_LOGIC;
		FifoStsRegAddr : OUT STD_LOGIC;
		IOCtrlRegAddr : OUT STD_LOGIC;
		nReset : OUT STD_LOGIC;
		CpldState : OUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END AddressDecoder;


--  Architecture Body

ARCHITECTURE AddressDecoder_architecture OF AddressDecoder IS	
	SIGNAL ResetFifo:STD_LOGIC;
BEGIN
	CpldState<='0';
	--板卡地址为0x300~0x30F;
	CS_D<=NOT(SA(9) AND SA(8) AND(NOT SA(7)) AND(NOT SA(6)) AND(NOT SA(5)) AND(NOT SA(4)) AND(NOT AEN));
	--8254的地址为0x300~0x303;
	CS_8254<=NOT(SA(9) AND SA(8) AND(NOT SA(7)) AND(NOT SA(6)) AND(NOT SA(5)) AND(NOT SA(4)) AND(NOT SA(4)) AND(NOT SA(3)) AND(NOT SA(2)) AND(NOT AEN));
	--FIFO状态寄存器地址，地址304H
	FifoStsRegAddr<=NOT(SA(9) AND SA(8) AND(NOT SA(7)) AND(NOT SA(6)) AND(NOT SA(5)) AND(NOT SA(4)) AND(NOT SA(4)) AND(NOT SA(3)) AND SA(2) AND(NOT SA(1)) AND(NOT SA(0)) AND(NOT AEN));
	--中断允许寄存器，地址305H(IO地址)
	IERegAddr<=NOT(SA(9) AND SA(8) AND(NOT SA(7)) AND(NOT SA(6)) AND(NOT SA(5)) AND(NOT SA(4)) AND(NOT SA(4)) AND(NOT SA(3)) AND SA(2) AND(NOT SA(1)) AND SA(0) AND(NOT AEN));
	--中断状态寄存器，地址306(IO地址)
	ISRegAddr<=NOT(SA(9) AND SA(8) AND(NOT SA(7)) AND(NOT SA(6)) AND(NOT SA(5)) AND(NOT SA(4)) AND(NOT SA(4)) AND(NOT SA(3)) AND SA(2) AND SA(1) AND(NOT SA(0)) AND(NOT AEN));
	--IO方式控制寄存器，地址307H(IO地址)
	IOCtrlRegAddr<=NOT(SA(9) AND SA(8) AND(NOT SA(7)) AND(NOT SA(6)) AND(NOT SA(5)) AND(NOT SA(4)) AND(NOT SA(4)) AND(NOT SA(3)) AND SA(2) AND SA(1) AND SA(0));
	--FIFO的读地址308H
	RD_Fifo<=NOT(SA(9) AND SA(8) AND(NOT SA(7)) AND(NOT SA(6)) AND(NOT SA(5)) AND(NOT SA(4)) AND(NOT SA(4)) AND SA(3) AND (NOT SA(2)) AND(NOT SA(1)) AND(NOT SA(0)) AND(NOT AEN) AND (NOT IOR));
	--16位操作时Iocs16为'0',8位时为'1'
	IOCS16<=NOT(SA(9) AND SA(8) AND(NOT SA(7)) AND(NOT SA(6)) AND(NOT SA(5)) AND(NOT SA(4)) AND(NOT SA(4)) AND SA(3) AND (NOT SA(2)) AND(NOT SA(1)) AND(NOT SA(0)) AND(NOT AEN) AND (NOT SBHE));
	--复位FIFO状态,向地址地址304H写任意值
	ResetFifo<=NOT(SA(9) AND SA(8) AND(NOT SA(7)) AND(NOT SA(6)) AND(NOT SA(5)) AND(NOT SA(4)) AND(NOT SA(4)) AND(NOT SA(3)) AND SA(2) AND(NOT SA(1)) AND(NOT SA(0)) AND(NOT AEN) AND(NOT IOW));
	nReset<=ResetFifo AND (NOT(RESET));
END AddressDecoder_architecture;