adtofifo.vhd

关于对数据采集卡的基于PC104总线的读写程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--  Entity Declaration
ENTITY AdToFifo IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		Clk : IN STD_LOGIC;
		Int : IN STD_LOGIC_VECTOR(3 downto 0);
		nReset : IN STD_LOGIC;
		ReadAd : OUT STD_LOGIC_VECTOR(3 downto 0);
		WriteFifo : OUT STD_LOGIC;
		ChannelVector : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END AdToFifo;
--  Architecture Body

ARCHITECTURE AdToFifo_architecture OF AdToFifo IS	
	SIGNAL qn:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL Flag:STD_LOGIC;
	SIGNAL result1,result2:STD_LOGIC;
BEGIN
		ChannelVector<=qn(7 DOWNTO 4);
	PROCESS(nReset,Clk)
	BEGIN
		IF(nReset='0')THEN
			Flag<='0';
			qn<="00000000";
		ELSIF(Clk'EVENT AND Clk='1')THEN
			IF(Int="0000")THEN
				Flag<='1';
			END IF;
			IF(Flag='1')THEN
				IF(qn="11111111")THEN
					qn<="00000000";
					Flag<='0';
				ELSE 
					qn<=qn+'1';
				END IF;
			END IF;
		END IF;
	END PROCESS;	

	PROCESS(nReset,qn(0))
	BEGIN
		IF(nReset='0')THEN
			result1<='0';result2<='0';
		ELSE
			IF(qn(3 DOWNTO 0)="0100")THEN
				result1<='1';
			END IF;
			IF(qn(3 DOWNTO 0)="1001")THEN
				result1<='0';
			END IF;
			IF(qn(3 DOWNTO 0)="0101")THEN
				result2<='1';
			END IF;
			IF(qn(3 DOWNTO 0)="1000")THEN
				result2<='0';
			END IF;
		END IF;
	END PROCESS;
	
	PROCESS(nReset,result1)
	VARIABLE Sel:STD_LOGIC_VECTOR(1 DOWNTO 0);
	BEGIN
		Sel:=qn(7)&qn(6);
		IF(nReset='0')THEN
			ReadAd<="1111";
		ELSIF(result1='1')THEN
			CASE Sel IS
				WHEN "00"=>ReadAd<="1110";
				WHEN "01"=>ReadAd<="1101";
				WHEN "10"=>ReadAd<="1011";
				WHEN "11"=>ReadAd<="0111";
				WHEN OTHERS=>ReadAd<="1111";
			END CASE;
		ELSE 
			ReadAd<="1111";
		END IF;
	END PROCESS;
	
	PROCESS(nReset,result2)
	BEGIN
		IF(nReset='0')THEN
			WriteFifo<='1';
		ELSIF(result2='1')THEN
			WriteFifo<='0';
		ELSE
			WriteFifo<='1';
		END IF;
	END PROCESS;
END AdToFifo_architecture;