workonebeta.fit.qmsg

Verilog实现的DDS正弦信号发生器和测频测相模块

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.446 ns register memory " "Info: Estimated most critical path is register to memory delay of 3.446 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Adjust:AdjustU0\|rSetPhase\[1\] 1 REG LAB_X16_Y10 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y10; Fanout = 6; REG Node = 'Adjust:AdjustU0\|rSetPhase\[1\]'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Adjust:AdjustU0|rSetPhase[1] } "NODE_NAME" } } { "Adjust.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Adjust.v" 107 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.590 ns) 1.423 ns Adjust:AdjustU0\|rSetPhase\[1\]~_wirecell 2 COMB LAB_X15_Y9 10 " "Info: 2: + IC(0.833 ns) + CELL(0.590 ns) = 1.423 ns; Loc. = LAB_X15_Y9; Fanout = 10; COMB Node = 'Adjust:AdjustU0\|rSetPhase\[1\]~_wirecell'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.423 ns" { Adjust:AdjustU0|rSetPhase[1] Adjust:AdjustU0|rSetPhase[1]~_wirecell } "NODE_NAME" } } { "Adjust.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Adjust.v" 107 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.640 ns) + CELL(0.383 ns) 3.446 ns Adapter:AdapterU0\|PhaseFindTable:PhaseFindTableU0\|altsyncram:altsyncram_component\|altsyncram_4331:auto_generated\|ram_block1a0~porta_address_reg1 3 MEM M4K_X13_Y10 1 " "Info: 3: + IC(1.640 ns) + CELL(0.383 ns) = 3.446 ns; Loc. = M4K_X13_Y10; Fanout = 1; MEM Node = 'Adapter:AdapterU0\|PhaseFindTable:PhaseFindTableU0\|altsyncram:altsyncram_component\|altsyncram_4331:auto_generated\|ram_block1a0~porta_address_reg1'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "2.023 ns" { Adjust:AdjustU0|rSetPhase[1]~_wirecell Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0|altsyncram:altsyncram_component|altsyncram_4331:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } } { "db/altsyncram_4331.tdf" "" { Text "F:/电赛/Quartus/WorkOneBetaC/db/altsyncram_4331.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.973 ns ( 28.24 % ) " "Info: Total cell delay = 0.973 ns ( 28.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.473 ns ( 71.76 % ) " "Info: Total interconnect delay = 2.473 ns ( 71.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "3.446 ns" { Adjust:AdjustU0|rSetPhase[1] Adjust:AdjustU0|rSetPhase[1]~_wirecell Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0|altsyncram:altsyncram_component|altsyncram_4331:auto_generated|ram_block1a0~porta_address_reg1 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "6 6 " "Info: Average interconnect usage is 6% of the available device resources. Peak interconnect usage is 6%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X14_Y0 X27_Y14 " "Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "Read:ReadU0\|rReadyFlag~0 " "Info: Node Read:ReadU0\|rReadyFlag~0 uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[55\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[55\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[55] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[55] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[103\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[103\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[103] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[103] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[63\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[63\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[63] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[63] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[102\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[102\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[102] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[102] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[111\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[111\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[111] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[111] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[54\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[54\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[54] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[54] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[110\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[110\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[110] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[110] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[62\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[62\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[62] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[62] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[95\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[95\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[95] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[95] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[93\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[93\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[93] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[93] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[91\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[91\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[91] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[91] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear Read:ReadU0\|SourceData\[83\] " "Info: Port clear -- assigned as a global for destination node Read:ReadU0\|SourceData\[83\] -- routed using non-global resources" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[83] } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|SourceData[83] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0}  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|rReadyFlag~0 } "NODE_NAME" } } { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 83 -1 0 } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Read:ReadU0|rReadyFlag~0 } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "7 " "Warning: Following 7 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "U4Dir VCC " "Info: Pin U4Dir has VCC driving its datain port" {  } { { "WorkOne.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 63 -1 0 } } { "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "U4Dir" } } } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U4Dir } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U4Dir } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "U5Dir VCC " "Info: Pin U5Dir has VCC driving its datain port" {  } { { "WorkOne.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 64 -1 0 } } { "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "U5Dir" } } } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U5Dir } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U5Dir } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "U6Dir VCC " "Info: Pin U6Dir has VCC driving its datain port" {  } { { "WorkOne.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 65 -1 0 } } { "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "U6Dir" } } } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U6Dir } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U6Dir } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "U7Dir GND " "Info: Pin U7Dir has GND driving its datain port" {  } { { "WorkOne.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 66 -1 0 } } { "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "U7Dir" } } } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U7Dir } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U7Dir } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "U9Dir VCC " "Info: Pin U9Dir has VCC driving its datain port" {  } { { "WorkOne.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 67 -1 0 } } { "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "U9Dir" } } } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U9Dir } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U9Dir } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "U10Dir VCC " "Info: Pin U10Dir has VCC driving its datain port" {  } { { "WorkOne.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 68 -1 0 } } { "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "U10Dir" } } } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U10Dir } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U10Dir } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "U11Dir GND " "Info: Pin U11Dir has GND driving its datain port" {  } { { "WorkOne.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 69 -1 0 } } { "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "U11Dir" } } } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U11Dir } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { U11Dir } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/电赛/Quartus/WorkOneBetaC/WorkOneBeta.fit.smsg " "Info: Generated suppressed messages file F:/电赛/Quartus/WorkOneBetaC/WorkOneBeta.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "179 " "Info: Allocated 179 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 21 22:08:34 2007 " "Info: Processing ended: Tue Aug 21 22:08:34 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}