workonebeta.hier_info

Verilog实现的DDS正弦信号发生器和测频测相模块

address_a[9] => altsyncram_v531:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_v531:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_v531:auto_generated.q_a[0]
q_a[1] <= altsyncram_v531:auto_generated.q_a[1]
q_a[2] <= altsyncram_v531:auto_generated.q_a[2]
q_a[3] <= altsyncram_v531:auto_generated.q_a[3]
q_a[4] <= altsyncram_v531:auto_generated.q_a[4]
q_a[5] <= altsyncram_v531:auto_generated.q_a[5]
q_a[6] <= altsyncram_v531:auto_generated.q_a[6]
q_a[7] <= altsyncram_v531:auto_generated.q_a[7]
q_a[8] <= altsyncram_v531:auto_generated.q_a[8]
q_a[9] <= altsyncram_v531:auto_generated.q_a[9]
q_a[10] <= altsyncram_v531:auto_generated.q_a[10]
q_a[11] <= altsyncram_v531:auto_generated.q_a[11]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT


|TopLayer|Measure:MeasureU0
Reset => rCountFinishFlag~3.IN0
Reset => rStartExsitFlag.ACLR
Reset => rFreClockCounter[31]~0.IN0
Reset => rFreClockCounter[31].ENA
Reset => rFreClockCounter[30].ENA
Reset => rFreClockCounter[29].ENA
Reset => rFreClockCounter[28].ENA
Reset => rFreClockCounter[27].ENA
Reset => rFreClockCounter[26].ENA
Reset => rFreClockCounter[25].ENA
Reset => rFreClockCounter[24].ENA
Reset => rFreClockCounter[23].ENA
Reset => rFreClockCounter[22].ENA
Reset => rFreClockCounter[21].ENA
Reset => rFreClockCounter[20].ENA
Reset => rFreClockCounter[19].ENA
Reset => rFreClockCounter[18].ENA
Reset => rFreClockCounter[17].ENA
Reset => rFreClockCounter[16].ENA
Reset => rFreClockCounter[15].ENA
Reset => rFreClockCounter[14].ENA
Reset => rFreClockCounter[13].ENA
Reset => rFreClockCounter[12].ENA
Reset => rFreClockCounter[11].ENA
Reset => rFreClockCounter[10].ENA
Reset => rFreClockCounter[9].ENA
Reset => rFreClockCounter[8].ENA
Reset => rFreClockCounter[7].ENA
Reset => rFreClockCounter[6].ENA
Reset => rFreClockCounter[5].ENA
Reset => rFreClockCounter[4].ENA
Reset => rFreClockCounter[3].ENA
Reset => rFreClockCounter[2].ENA
Reset => rFreClockCounter[1].ENA
Reset => rFreClockCounter[0].ENA
Reset => rPhaseClockCounter[31].ENA
Reset => rPhaseClockCounter[30].ENA
Reset => rPhaseClockCounter[29].ENA
Reset => rPhaseClockCounter[28].ENA
Reset => rPhaseClockCounter[27].ENA
Reset => rPhaseClockCounter[26].ENA
Reset => rPhaseClockCounter[25].ENA
Reset => rPhaseClockCounter[24].ENA
Reset => rPhaseClockCounter[23].ENA
Reset => rPhaseClockCounter[22].ENA
Reset => rPhaseClockCounter[21].ENA
Reset => rPhaseClockCounter[20].ENA
Reset => rPhaseClockCounter[19].ENA
Reset => rPhaseClockCounter[18].ENA
Reset => rPhaseClockCounter[17].ENA
Reset => rPhaseClockCounter[16].ENA
Reset => rPhaseClockCounter[15].ENA
Reset => rPhaseClockCounter[14].ENA
Reset => rPhaseClockCounter[13].ENA
Reset => rPhaseClockCounter[12].ENA
Reset => rPhaseClockCounter[11].ENA
Reset => rPhaseClockCounter[10].ENA
Reset => rPhaseClockCounter[9].ENA
Reset => rPhaseClockCounter[8].ENA
Reset => rPhaseClockCounter[7].ENA
Reset => rPhaseClockCounter[6].ENA
Reset => rPhaseClockCounter[5].ENA
Reset => rPhaseClockCounter[4].ENA
Reset => rPhaseClockCounter[3].ENA
Reset => rPhaseClockCounter[2].ENA
Reset => rPhaseClockCounter[1].ENA
Reset => rPhaseClockCounter[0].ENA
Start => rCountFinishFlag~3.IN1
Start => rFreClockCounter[31]~0.IN1
Start => rFreWaveCounter[31].ACLR
Start => rFreWaveCounter[30].ACLR
Start => rFreWaveCounter[29].ACLR
Start => rFreWaveCounter[28].ACLR
Start => rFreWaveCounter[27].ACLR
Start => rFreWaveCounter[26].ACLR
Start => rFreWaveCounter[25].ACLR
Start => rFreWaveCounter[24].ACLR
Start => rFreWaveCounter[23].ACLR
Start => rFreWaveCounter[22].ACLR
Start => rFreWaveCounter[21].ACLR
Start => rFreWaveCounter[20].ACLR
Start => rFreWaveCounter[19].ACLR
Start => rFreWaveCounter[18].ACLR
Start => rFreWaveCounter[17].ACLR
Start => rFreWaveCounter[16].ACLR
Start => rFreWaveCounter[15].ACLR
Start => rFreWaveCounter[14].ACLR
Start => rFreWaveCounter[13].ACLR
Start => rFreWaveCounter[12].ACLR
Start => rFreWaveCounter[11].ACLR
Start => rFreWaveCounter[10].ACLR
Start => rFreWaveCounter[9].ACLR
Start => rFreWaveCounter[8].ACLR
Start => rFreWaveCounter[7].ACLR
Start => rFreWaveCounter[6].ACLR
Start => rFreWaveCounter[5].ACLR
Start => rFreWaveCounter[4].ACLR
Start => rFreWaveCounter[3].ACLR
Start => rFreWaveCounter[2].ACLR
Start => rFreWaveCounter[1].ACLR
Start => rFreWaveCounter[0].ACLR
Start => rPhaseWaveCounter[31].ACLR
Start => rPhaseWaveCounter[30].ACLR
Start => rPhaseWaveCounter[29].ACLR
Start => rPhaseWaveCounter[28].ACLR
Start => rPhaseWaveCounter[27].ACLR
Start => rPhaseWaveCounter[26].ACLR
Start => rPhaseWaveCounter[25].ACLR
Start => rPhaseWaveCounter[24].ACLR
Start => rPhaseWaveCounter[23].ACLR
Start => rPhaseWaveCounter[22].ACLR
Start => rPhaseWaveCounter[21].ACLR
Start => rPhaseWaveCounter[20].ACLR
Start => rPhaseWaveCounter[19].ACLR
Start => rPhaseWaveCounter[18].ACLR
Start => rPhaseWaveCounter[17].ACLR
Start => rPhaseWaveCounter[16].ACLR
Start => rPhaseWaveCounter[15].ACLR
Start => rPhaseWaveCounter[14].ACLR
Start => rPhaseWaveCounter[13].ACLR
Start => rPhaseWaveCounter[12].ACLR
Start => rPhaseWaveCounter[11].ACLR
Start => rPhaseWaveCounter[10].ACLR
Start => rPhaseWaveCounter[9].ACLR
Start => rPhaseWaveCounter[8].ACLR
Start => rPhaseWaveCounter[7].ACLR
Start => rPhaseWaveCounter[6].ACLR
Start => rPhaseWaveCounter[5].ACLR
Start => rPhaseWaveCounter[4].ACLR
Start => rPhaseWaveCounter[3].ACLR
Start => rPhaseWaveCounter[2].ACLR
Start => rPhaseWaveCounter[1].ACLR
Start => rPhaseWaveCounter[0].ACLR
Start => rIndicatorLightB.ENA
Clock => Clock~0.IN1
InputWaveOne => rFreWaveCounter[31].CLK
InputWaveOne => rFreWaveCounter[30].CLK
InputWaveOne => rFreWaveCounter[29].CLK
InputWaveOne => rFreWaveCounter[28].CLK
InputWaveOne => rFreWaveCounter[27].CLK
InputWaveOne => rFreWaveCounter[26].CLK
InputWaveOne => rFreWaveCounter[25].CLK
InputWaveOne => rFreWaveCounter[24].CLK
InputWaveOne => rFreWaveCounter[23].CLK
InputWaveOne => rFreWaveCounter[22].CLK
InputWaveOne => rFreWaveCounter[21].CLK
InputWaveOne => rFreWaveCounter[20].CLK
InputWaveOne => rFreWaveCounter[19].CLK
InputWaveOne => rFreWaveCounter[18].CLK
InputWaveOne => rFreWaveCounter[17].CLK
InputWaveOne => rFreWaveCounter[16].CLK
InputWaveOne => rFreWaveCounter[15].CLK
InputWaveOne => rFreWaveCounter[14].CLK
InputWaveOne => rFreWaveCounter[13].CLK
InputWaveOne => rFreWaveCounter[12].CLK
InputWaveOne => rFreWaveCounter[11].CLK
InputWaveOne => rFreWaveCounter[10].CLK
InputWaveOne => rFreWaveCounter[9].CLK
InputWaveOne => rFreWaveCounter[8].CLK
InputWaveOne => rFreWaveCounter[7].CLK