workonebeta.hier_info

Verilog实现的DDS正弦信号发生器和测频测相模块

Clock => Base[4]~reg0.CLK
Clock => Base[3]~reg0.CLK
Clock => Base[2]~reg0.CLK
Clock => Base[1]~reg0.CLK
Clock => Base[0]~reg0.CLK
Base[0] <= Base[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[1] <= Base[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[2] <= Base[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[3] <= Base[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[4] <= Base[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[5] <= Base[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[6] <= Base[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[7] <= Base[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[8] <= Base[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[9] <= Base[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[10] <= Base[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[11] <= Base[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[12] <= Base[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[13] <= Base[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[14] <= Base[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[15] <= Base[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[16] <= Base[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[17] <= Base[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[18] <= Base[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[19] <= Base[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[20] <= Base[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[21] <= Base[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[22] <= Base[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[23] <= Base[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[24] <= Base[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[25] <= Base[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[26] <= Base[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[27] <= Base[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[28] <= Base[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Base[29] <= Base[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Increment[0] => Add0.IN60
Increment[1] => Add0.IN59
Increment[2] => Add0.IN58
Increment[3] => Add0.IN57
Increment[4] => Add0.IN56
Increment[5] => Add0.IN55
Increment[6] => Add0.IN54
Increment[7] => Add0.IN53
Increment[8] => Add0.IN52
Increment[9] => Add0.IN51
Increment[10] => Add0.IN50
Increment[11] => Add0.IN49
Increment[12] => Add0.IN48
Increment[13] => Add0.IN47
Increment[14] => Add0.IN46
Increment[15] => Add0.IN45
Increment[16] => Add0.IN44
Increment[17] => Add0.IN43
Increment[18] => Add0.IN42
Increment[19] => Add0.IN41
Increment[20] => Add0.IN40
Increment[21] => Add0.IN39


|TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0
address[0] => address[0]~9.IN1
address[1] => address[1]~8.IN1
address[2] => address[2]~7.IN1
address[3] => address[3]~6.IN1
address[4] => address[4]~5.IN1
address[5] => address[5]~4.IN1
address[6] => address[6]~3.IN1
address[7] => address[7]~2.IN1
address[8] => address[8]~1.IN1
address[9] => address[9]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a


|TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_v531:auto_generated.address_a[0]
address_a[1] => altsyncram_v531:auto_generated.address_a[1]
address_a[2] => altsyncram_v531:auto_generated.address_a[2]
address_a[3] => altsyncram_v531:auto_generated.address_a[3]
address_a[4] => altsyncram_v531:auto_generated.address_a[4]
address_a[5] => altsyncram_v531:auto_generated.address_a[5]
address_a[6] => altsyncram_v531:auto_generated.address_a[6]
address_a[7] => altsyncram_v531:auto_generated.address_a[7]
address_a[8] => altsyncram_v531:auto_generated.address_a[8]
address_a[9] => altsyncram_v531:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_v531:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_v531:auto_generated.q_a[0]
q_a[1] <= altsyncram_v531:auto_generated.q_a[1]
q_a[2] <= altsyncram_v531:auto_generated.q_a[2]
q_a[3] <= altsyncram_v531:auto_generated.q_a[3]
q_a[4] <= altsyncram_v531:auto_generated.q_a[4]
q_a[5] <= altsyncram_v531:auto_generated.q_a[5]
q_a[6] <= altsyncram_v531:auto_generated.q_a[6]
q_a[7] <= altsyncram_v531:auto_generated.q_a[7]
q_a[8] <= altsyncram_v531:auto_generated.q_a[8]
q_a[9] <= altsyncram_v531:auto_generated.q_a[9]
q_a[10] <= altsyncram_v531:auto_generated.q_a[10]
q_a[11] <= altsyncram_v531:auto_generated.q_a[11]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT


|TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1
address[0] => address[0]~9.IN1
address[1] => address[1]~8.IN1
address[2] => address[2]~7.IN1
address[3] => address[3]~6.IN1
address[4] => address[4]~5.IN1
address[5] => address[5]~4.IN1
address[6] => address[6]~3.IN1
address[7] => address[7]~2.IN1
address[8] => address[8]~1.IN1
address[9] => address[9]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a


|TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_v531:auto_generated.address_a[0]
address_a[1] => altsyncram_v531:auto_generated.address_a[1]
address_a[2] => altsyncram_v531:auto_generated.address_a[2]
address_a[3] => altsyncram_v531:auto_generated.address_a[3]
address_a[4] => altsyncram_v531:auto_generated.address_a[4]
address_a[5] => altsyncram_v531:auto_generated.address_a[5]
address_a[6] => altsyncram_v531:auto_generated.address_a[6]
address_a[7] => altsyncram_v531:auto_generated.address_a[7]
address_a[8] => altsyncram_v531:auto_generated.address_a[8]