workonebeta.hier_info

Verilog实现的DDS正弦信号发生器和测频测相模块

address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[9] => ram_block1a16.PORTAADDR9
address_a[9] => ram_block1a17.PORTAADDR9
address_a[9] => ram_block1a18.PORTAADDR9
address_a[9] => ram_block1a19.PORTAADDR9
address_a[9] => ram_block1a20.PORTAADDR9
address_a[9] => ram_block1a21.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT
q_a[16] <= ram_block1a16.PORTADATAOUT
q_a[17] <= ram_block1a17.PORTADATAOUT
q_a[18] <= ram_block1a18.PORTADATAOUT
q_a[19] <= ram_block1a19.PORTADATAOUT
q_a[20] <= ram_block1a20.PORTADATAOUT
q_a[21] <= ram_block1a21.PORTADATAOUT


|TopLayer|Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0
address[0] => address[0]~8.IN1
address[1] => address[1]~7.IN1
address[2] => address[2]~6.IN1
address[3] => address[3]~5.IN1
address[4] => address[4]~4.IN1
address[5] => address[5]~3.IN1
address[6] => address[6]~2.IN1
address[7] => address[7]~1.IN1
address[8] => address[8]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a


|TopLayer|Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_4331:auto_generated.address_a[0]
address_a[1] => altsyncram_4331:auto_generated.address_a[1]
address_a[2] => altsyncram_4331:auto_generated.address_a[2]
address_a[3] => altsyncram_4331:auto_generated.address_a[3]
address_a[4] => altsyncram_4331:auto_generated.address_a[4]
address_a[5] => altsyncram_4331:auto_generated.address_a[5]
address_a[6] => altsyncram_4331:auto_generated.address_a[6]
address_a[7] => altsyncram_4331:auto_generated.address_a[7]
address_a[8] => altsyncram_4331:auto_generated.address_a[8]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_4331:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_4331:auto_generated.q_a[0]
q_a[1] <= altsyncram_4331:auto_generated.q_a[1]
q_a[2] <= altsyncram_4331:auto_generated.q_a[2]
q_a[3] <= altsyncram_4331:auto_generated.q_a[3]
q_a[4] <= altsyncram_4331:auto_generated.q_a[4]
q_a[5] <= altsyncram_4331:auto_generated.q_a[5]
q_a[6] <= altsyncram_4331:auto_generated.q_a[6]
q_a[7] <= altsyncram_4331:auto_generated.q_a[7]
q_a[8] <= altsyncram_4331:auto_generated.q_a[8]
q_a[9] <= altsyncram_4331:auto_generated.q_a[9]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|TopLayer|Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0|altsyncram:altsyncram_component|altsyncram_4331:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT


|TopLayer|DDS:DDSU0
Clock => Clock~0.IN3
FrequencyKey[0] => FrequencyKey[0]~21.IN1
FrequencyKey[1] => FrequencyKey[1]~20.IN1
FrequencyKey[2] => FrequencyKey[2]~19.IN1
FrequencyKey[3] => FrequencyKey[3]~18.IN1
FrequencyKey[4] => FrequencyKey[4]~17.IN1
FrequencyKey[5] => FrequencyKey[5]~16.IN1
FrequencyKey[6] => FrequencyKey[6]~15.IN1
FrequencyKey[7] => FrequencyKey[7]~14.IN1
FrequencyKey[8] => FrequencyKey[8]~13.IN1
FrequencyKey[9] => FrequencyKey[9]~12.IN1
FrequencyKey[10] => FrequencyKey[10]~11.IN1
FrequencyKey[11] => FrequencyKey[11]~10.IN1
FrequencyKey[12] => FrequencyKey[12]~9.IN1
FrequencyKey[13] => FrequencyKey[13]~8.IN1
FrequencyKey[14] => FrequencyKey[14]~7.IN1
FrequencyKey[15] => FrequencyKey[15]~6.IN1
FrequencyKey[16] => FrequencyKey[16]~5.IN1
FrequencyKey[17] => FrequencyKey[17]~4.IN1
FrequencyKey[18] => FrequencyKey[18]~3.IN1
FrequencyKey[19] => FrequencyKey[19]~2.IN1
FrequencyKey[20] => FrequencyKey[20]~1.IN1
FrequencyKey[21] => FrequencyKey[21]~0.IN1
PhaseKey[0] => Add0.IN10
PhaseKey[1] => Add0.IN9
PhaseKey[2] => Add0.IN8
PhaseKey[3] => Add0.IN7
PhaseKey[4] => Add0.IN6
PhaseKey[5] => Add0.IN5
PhaseKey[6] => Add0.IN4
PhaseKey[7] => Add0.IN3
PhaseKey[8] => Add0.IN2
PhaseKey[9] => Add0.IN1
ClockOut <= Clock~0.DB_MAX_OUTPUT_PORT_TYPE
WaveOutOne[0] <= SinFindTable:SinFindTableU0.q
WaveOutOne[1] <= SinFindTable:SinFindTableU0.q
WaveOutOne[2] <= SinFindTable:SinFindTableU0.q
WaveOutOne[3] <= SinFindTable:SinFindTableU0.q
WaveOutOne[4] <= SinFindTable:SinFindTableU0.q
WaveOutOne[5] <= SinFindTable:SinFindTableU0.q
WaveOutOne[6] <= SinFindTable:SinFindTableU0.q
WaveOutOne[7] <= SinFindTable:SinFindTableU0.q
WaveOutOne[8] <= SinFindTable:SinFindTableU0.q
WaveOutOne[9] <= SinFindTable:SinFindTableU0.q
WaveOutOne[10] <= SinFindTable:SinFindTableU0.q
WaveOutOne[11] <= SinFindTable:SinFindTableU0.q
WaveOutTwo[0] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[1] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[2] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[3] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[4] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[5] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[6] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[7] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[8] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[9] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[10] <= SinFindTable:SinFindTableU1.q
WaveOutTwo[11] <= SinFindTable:SinFindTableU1.q


|TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0
Clock => Base[29]~reg0.CLK
Clock => Base[28]~reg0.CLK
Clock => Base[27]~reg0.CLK
Clock => Base[26]~reg0.CLK
Clock => Base[25]~reg0.CLK
Clock => Base[24]~reg0.CLK
Clock => Base[23]~reg0.CLK
Clock => Base[22]~reg0.CLK
Clock => Base[21]~reg0.CLK
Clock => Base[20]~reg0.CLK
Clock => Base[19]~reg0.CLK
Clock => Base[18]~reg0.CLK
Clock => Base[17]~reg0.CLK
Clock => Base[16]~reg0.CLK
Clock => Base[15]~reg0.CLK
Clock => Base[14]~reg0.CLK
Clock => Base[13]~reg0.CLK
Clock => Base[12]~reg0.CLK
Clock => Base[11]~reg0.CLK
Clock => Base[10]~reg0.CLK
Clock => Base[9]~reg0.CLK
Clock => Base[8]~reg0.CLK
Clock => Base[7]~reg0.CLK
Clock => Base[6]~reg0.CLK
Clock => Base[5]~reg0.CLK