workonebeta.map.qmsg

Verilog实现的DDS正弦信号发生器和测频测相模块

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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SinFindTable.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SinFindTable.v" { { "Info" "ISGN_ENTITY_NAME" "1 SinFindTable " "Info: Found entity 1: SinFindTable" {  } { { "SinFindTable.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/SinFindTable.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "TopLayer " "Info: Elaborating entity \"TopLayer\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Adjust Adjust:AdjustU0 " "Info: Elaborating entity \"Adjust\" for hierarchy \"Adjust:AdjustU0\"" {  } { { "WorkOne.v" "AdjustU0" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 135 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Strobe Adjust:AdjustU0\|Strobe:ScanClockDivider " "Info: Elaborating entity \"Strobe\" for hierarchy \"Adjust:AdjustU0\|Strobe:ScanClockDivider\"" {  } { { "Adjust.v" "ScanClockDivider" { Text "F:/电赛/Quartus/WorkOneBetaC/Adjust.v" 43 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Adapter Adapter:AdapterU0 " "Info: Elaborating entity \"Adapter\" for hierarchy \"Adapter:AdapterU0\"" {  } { { "WorkOne.v" "AdapterU0" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 145 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FreFindTable Adapter:AdapterU0\|FreFindTable:FreFindTableU0 " "Info: Elaborating entity \"FreFindTable\" for hierarchy \"Adapter:AdapterU0\|FreFindTable:FreFindTableU0\"" {  } { { "Adapter.v" "FreFindTableU0" { Text "F:/电赛/Quartus/WorkOneBetaC/Adapter.v" 21 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/program files/quartus ii/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/program files/quartus ii/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/program files/quartus ii/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component\"" {  } { { "FreFindTable.v" "altsyncram_component" { Text "F:/电赛/Quartus/WorkOneBetaC/FreFindTable.v" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component\"" {  } { { "FreFindTable.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/FreFindTable.v" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fp21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fp21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fp21 " "Info: Found entity 1: altsyncram_fp21" {  } { { "db/altsyncram_fp21.tdf" "" { Text "F:/电赛/Quartus/WorkOneBetaC/db/altsyncram_fp21.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fp21 Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component\|altsyncram_fp21:auto_generated " "Info: Elaborating entity \"altsyncram_fp21\" for hierarchy \"Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component\|altsyncram_fp21:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/program files/quartus ii/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PhaseFindTable Adapter:AdapterU0\|PhaseFindTable:PhaseFindTableU0 " "Info: Elaborating entity \"PhaseFindTable\" for hierarchy \"Adapter:AdapterU0\|PhaseFindTable:PhaseFindTableU0\"" {  } { { "Adapter.v" "PhaseFindTableU0" { Text "F:/电赛/Quartus/WorkOneBetaC/Adapter.v" 22 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}