workonebeta.map.qmsg

Verilog实现的DDS正弦信号发生器和测频测相模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 21 22:08:15 2007 " "Info: Processing started: Tue Aug 21 22:08:15 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off WorkOneBeta -c WorkOneBeta " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off WorkOneBeta -c WorkOneBeta" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "WorkOne.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file WorkOne.v" { { "Info" "ISGN_ENTITY_NAME" "1 TopLayer " "Info: Found entity 1: TopLayer" {  } { { "WorkOne.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Adjust.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Adjust.v" { { "Info" "ISGN_ENTITY_NAME" "1 Adjust " "Info: Found entity 1: Adjust" {  } { { "Adjust.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Adjust.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Adapter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 Adapter " "Info: Found entity 1: Adapter" {  } { { "Adapter.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Adapter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Read.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Read.v" { { "Info" "ISGN_ENTITY_NAME" "1 Read " "Info: Found entity 1: Read" {  } { { "Read.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Read.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Measure.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Measure.v" { { "Info" "ISGN_ENTITY_NAME" "1 Measure " "Info: Found entity 1: Measure" {  } { { "Measure.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Measure.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "Strobe.v(17) " "Warning (10268): Verilog HDL information at Strobe.v(17): Always Construct contains both blocking and non-blocking assignments" {  } { { "Strobe.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Strobe.v" 17 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Strobe.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Strobe.v" { { "Info" "ISGN_ENTITY_NAME" "1 Strobe " "Info: Found entity 1: Strobe" {  } { { "Strobe.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Strobe.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DDS.v" { { "Info" "ISGN_ENTITY_NAME" "1 DDS " "Info: Found entity 1: DDS" {  } { { "DDS.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/DDS.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Accumulater.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Accumulater.v" { { "Info" "ISGN_ENTITY_NAME" "1 Accumulater " "Info: Found entity 1: Accumulater" {  } { { "Accumulater.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Accumulater.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FreFindTable.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FreFindTable.v" { { "Info" "ISGN_ENTITY_NAME" "1 FreFindTable " "Info: Found entity 1: FreFindTable" {  } { { "FreFindTable.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/FreFindTable.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}