config_control_signals.v

来自「采用CPLD来培植ALTERA公司的CYCLONE系列FPGA」· Verilog 代码 · 共 20 行

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//--                                                                           	--
//-- Title		: config_control_signal.v       	 							--
//-- Modified	: 04/09/2005                                                 	--
//-- Author		: Altera Component Applications                                 -- 
//--                                                                           	--                                       	--
//--------------------------------------------------------------------------------
//--                                                                           
//-- Description: 	This design allows for configuration from multiple pages     
//--              	with either the Stratix PGM pins (remote/local) or the Dipswitch (MPGM pins)
//--				as the page select source(non-remote/local). 
//--				It can configure stratix II board. Some customization of the code is required 
//--				in order to work on specified board. Please refer to below description.
//--
//-- 	
//--	Refer to readme documentation for details on functionality of this design.                       
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//
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//--Copyright