header.v

来自「采用CPLD来培植ALTERA公司的CYCLONE系列FPGA」· Verilog 代码 · 共 46 行

// header.v

//*************************
//	Configuration Schemes
//*************************
//`define PASSIVE_SERIAL
`define FAST_PASSIVE_PARALLEL
//`define FAST_PASSIVE_PARALLEL_DECOMPRESSION
//`define PASSIVE_PARALLEL_ASY


//*************************
//	FPGA Device
//*************************
//`define STRATIX
`define STRATIX2


//*************************
//	Configuration Feature
//*************************
//`define INIT_DONE 	//INIT_DONE is turned on
`undef INIT_DONE		//INIT_DONE is turned off


//*****************************************
//Flash address width parameters
//*****************************************
`define ADDR_WIDTH_VALUE 27


//*****************************************
//Number of additional DCLK count after Configuration 
//*****************************************
`define INIT_DCLK_CNT_VALUE 8


//*****************************************
//Configuration Page Start Address
//*****************************************
`define PAGE_SAFE_VALUE 	27'h000000		//USER DEFINE Safe page start address
`define PAGE_USER_VALUE 	27'h500000		//USER DEFINE User page start address
`define PAGE_TWO_VALUE 		27'hA00000		//USER DEFINE Page two start address
`define PAGE_THREE_VALUE 	27'h000000		//USER DEFINE Page three start address
`define PAGE_FOUR_VALUE 	27'h000000		//USER DEFINE Page four start address