📄 clock_top2.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity clock_top2 is
port ( clk38,reset,setmin,sethour:in std_logic;
speaker: out std_logic;
lamp: out std_logic_vector(2 downto 0);
sel: out std_logic_vector(2 downto 0);
a,b,c,d,e,f,g: out std_logic);
end clock_top2;
--*************************************************
architecture a of clock_top2 is
--*************************************************
--second counter
COMPONENT second
PORT(
clk, reset11,setmin: IN STD_LOGIC;
daout: out std_logic_vector(6 downto 0);
enmin: OUT STD_LOGIC);
END COMPONENT;
--*************************************************
-- minute counter
COMPONENT minute
PORT(
clk,clk1,reset11,sethour: IN STD_LOGIC;
enhour: OUT STD_LOGIC;
daout: out std_logic_vector(6 downto 0));
END COMPONENT;
--*************************************************
--hour counter
COMPONENT hour
PORT(
clk, reset11: IN STD_LOGIC;
daout: out std_logic_vector(5 downto 0));
END COMPONENT;
--*************************************************
COMPONENT alert
PORT(
clk: IN STD_LOGIC;
dain:in std_logic_vector(6 downto 0);
lamp: out std_logic_vector(2 downto 0);
speak: OUT STD_LOGIC);
END COMPONENT;
--*************************************************
COMPONENT seltime
PORT(
clk1, reset11: IN STD_LOGIC;
sec,min:in std_logic_vector(6 downto 0);
hour:in std_logic_vector(5 downto 0);
daout: out std_logic_vector(3 downto 0);
sel: OUT STD_LOGIC_vector(2 downto 0));
END COMPONENT;
--*************************************************
COMPONENT deled
PORT(
num: IN STD_LOGIC_vector(3 downto 0);
led: out std_logic_vector(6 downto 0));
END COMPONENT;
COMPONENT count8
port(clk:in std_logic;
oc:out std_logic);
end COMPONENT;
--*************************************************
signal ledout: std_logic_vector(6 downto 0);
signal reset11,clk,clkdsp,enmin_re,enhour_re: std_logic;
signal second_daout,minute_daout:std_logic_vector(6 downto 0);
signal hour_daout:std_logic_vector(5 downto 0);
signal seltime_daout:std_logic_vector(3 downto 0);
--*************************************************
begin
a<=ledout(0);
b<=ledout(1);
c<=ledout(2);
d<=ledout(3);
e<=ledout(4);
f<=ledout(5);
g<=ledout(6);
reset11<=reset;
clkdsp<=clk38;
u1: second port map(
reset11 =>reset11,
clk =>clk,
setmin =>setmin,
enmin =>enmin_re,
daout =>second_daout);
u2:minute port map(
clk =>enmin_re,
clk1 =>clk,
reset11 =>reset11,
sethour =>sethour,
enhour =>enhour_re,
daout =>minute_daout);
u3:hour port map(
clk =>enhour_re,
reset11 =>reset11,
daout =>hour_daout);
u4:alert port map(
clk =>clk,
dain =>minute_daout,
speak =>speaker,
lamp =>lamp);
u5:seltime port map(
clk1 =>clkdsp,
reset11 =>reset11,
sec =>second_daout,
min =>minute_daout,
hour =>hour_daout,
daout =>seltime_daout,
sel =>sel);
u6:deled port map(
num =>seltime_daout,
led =>ledout);
u7: count8 port map(clk =>clk38,
oc =>clk);
end a;
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY second IS
PORT(
clk, reset11,setmin : IN STD_LOGIC;
enmin : OUT STD_LOGIC;
daout: out std_logic_vector (6 downto 0));
END entity second;
ARCHITECTURE fun OF second IS
SIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);
BEGIN
daout <= count;
process ( clk , reset11 , setmin)
begin
-- enmin<=k;
if (reset11='0') then
count <= "0000000";
elsif (setmin='0') then
enmin <= clk;
elsif (clk 'event and clk='1') then
if (count(3 downto 0)="1001") then
if (count <16#60#) then
if (count="1011001") then
enmin<='1';
count<="0000000";
ELSE
count<=count+7;
end if;
else
count<="0000000";
end if;
elsif (count < 16#60#) then
count <= count+1;
enmin<='0' after 100 ns;
else
count<="0000000";
end if;
end if;
end process;
END fun;
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY minute IS
PORT(
clk,clk1,reset11,sethour : IN STD_LOGIC;
enhour : OUT STD_LOGIC;
daout: out std_logic_vector (6 downto 0));
END entity minute;
ARCHITECTURE fun OF minute IS
SIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);
BEGIN
daout <= count;
process ( clk,reset11,sethour)
begin
if (reset11='0') then
count <= "0000000";
elsif (sethour='0') then
enhour <= clk1;
elsif (clk' event and clk='1') then
if (count(3 downto 0)="1001") then
if (count <16#60#) then
if (count="1011001") then
enhour<='1';
count<="0000000";
ELSE
count<=count+7;
end if;
else
count<="0000000";
end if;
elsif(count <16#60#) then
count <= count + 1;
enhour<='0' after 100 ns;
else
count<="0000000";
end if;
end if;
end process;
END fun;
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY hour IS
PORT(
clk,reset11: IN STD_LOGIC;
daout: out std_logic_vector (5 downto 0));
END entity hour;
ARCHITECTURE fun OF hour IS
SIGNAL count: STD_LOGIC_VECTOR( 5 downto 0);
BEGIN
daout <= count;
process ( clk,reset11)
begin
if (reset11='0') then
count <= "000000";
elsif (clk' event and clk='1') then
if (count(3 downto 0)="1001") then
if (count <16#24#) then
count<=count + 7;
else
count<="000000";
end if;
elsif(count <16#24#) then
count <= count + 1;
else
count<="000000";
end if;
end if;
end process;
END fun;
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY seltime IS
PORT(
clk1, reset11: IN STD_LOGIC;
sec,min : IN STD_LOGIC_VECTOR(6 downto 0);
hour : in std_logic_vector (5 downto 0);
daout : OUT STD_LOGIC_vector (3 downto 0);
sel : out std_logic_vector ( 2 downto 0));
END seltime;
ARCHITECTURE fun OF seltime IS
SIGNAL count: STD_LOGIC_vector ( 2 downto 0);
BEGIN
sel <= count;
process ( clk1,reset11)
begin
if (reset11 ='0') then
count <= "000";
elsif (clk1 'event and clk1='1') then
count <= count + 1;
end if;
case count is
when "000" => daout <= sec(3 downto 0);
when "001" => daout(3) <= '0';
daout(2 downto 0) <= sec (6 downto 4);
when "011" => daout <= min (3 downto 0);
when "100" => daout(3) <= '0';
daout(2 downto 0) <= min (6 downto 4);
when "110" => daout <= hour (3 downto 0);
when "111" => daout(3 downto 2) <= "00";
daout(1 downto 0) <= hour(5 downto 4);
when others => daout<="1111";
end case;
end process;
end fun;
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY alert IS
PORT(
clk : IN STD_LOGIC;
dain : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
speak: OUT STD_LOGIC;
lamp : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END alert ;
ARCHITECTURE fun OF alert IS
signal count : std_logic_vector( 1 downto 0);
signal count1: std_logic_vector( 1 downto 0);
BEGIN
speaker:process (clk)
begin
if (clk 'event and clk= '1') then
if (dain = "0000000") then
if (count1>="10") then
count1<="00";
else
count1 <= count1 + 1;
end if;
speak <= count1(1);
else
speak <= '0';
end if;
end if;
end process speaker;
lamper:process(clk)
begin
if (rising_edge(clk))then
if (dain = "0000000") then
if (count <= "10") then
if (count ="00") then
lamp <= "001" ;
elsif (count = "01") then
lamp <= "010" ;
elsif(count="10") then
lamp <= "100" ;
end if;
count <= count + 1;
else
count <= "00";
end if;
else
lamp<="000";
end if;
end if;
end process lamper;
END fun ;
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY deled IS
PORT(num: IN std_logic_vector( 3 downto 0);
led: OUT std_logic_vector(6 downto 0));
END deled;
ARCHITECTURE fun OF deled IS
BEGIN
led <= "0111111" when num= "0000" else
"0000110" when num= "0001" else
"1011011" when num= "0010" else
"1001111" when num= "0011" else
"1100110" when num= "0100" else
"1101101" when num= "0101" else
"1111101" when num= "0110" else
"0000111" when num= "0111" else
"1111111" when num= "1000" else
"1101111" when num= "1001" else
"1000000" ;
END fun;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count8 is
port(clk:in std_logic;
oc:out std_logic);
end;
architecture a of count8 is
signal q:integer range 0 to 305;
begin
process(clk)
begin
if(clk'event and clk='1')then
if q=305 then
q<=0;
else
q<=q+1;
end if;
end if;
if q<153 then
oc<='1';
else
oc<='0';
end if;
end process;
end;
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