m68k.vhd

motorola m68k VHDL描述

          when 3 => res := ccvar.sr(8) or ccvar.sr(10);
          when 4 => res := not(ccvar.sr(8));
          when 5 => res := ccvar.sr(8);
          when 6 => res := not(ccvar.sr(10));
          when 7 => res := ccvar.sr(10);
          when 8 => res := not(ccvar.sr(9));
          when 9 => res := ccvar.sr(9);
          when 10 => res := not(ccvar.sr(11));
          when 11 => res := ccvar.sr(11);
          when 12 => res := ((ccvar.sr(11) and ccvar.sr(9)) or (not(ccvar.sr(11)) and
not(ccvar.sr(9))));
          when 13 => res := ((ccvar.sr(11) and not(ccvar.sr(9))) or (not(ccvar.sr(11)) and ccvar.sr(9)));
          when 14 => res := (((ccvar.sr(11) and ccvar.sr(9)) or (not(ccvar.sr(11)) and not(ccvar.sr(9)))) and (not(ccvar.sr(10))));
          when 15 => res := ((ccvar.sr(10) or (ccvar.sr(11) and not(ccvar.sr(9)))) or
(not(ccvar.sr(11)) and ccvar.sr(9)));
          when others => null;
        end case;
end cc;


procedure scc(sccvar :inout var_record) is
variable result : bit_vector(31 downto 0);
variable res : bit;
variable sccdummy: bit_vector(1 downto 0) := "00";
variable sccdummy2: bit_vector(31 downto 0);
begin
  write(L,ret_string("Arrived at Scc instruction"));
  writeline(outfile,L);
        opr_fetch(sccvar,sccdummy,sccvar.ir(5 downto 3),sccvar.ir(2 downto 0),result);
        cc(sccvar,sccvar.ir(11 downto 8),res);
        case res is
          when '0' =>
                sccdummy2 := x"00000000";
                opr_write(sccvar,sccdummy,sccvar.ir(5 downto 3),sccvar.ir(2 downto 0),sccdummy2);
          when '1' =>
                sccdummy2 := x"000000ff";
                opr_write(sccvar,sccdummy,sccvar.ir(5 downto 3),sccvar.ir(2 downto 0),sccdummy2);
        end case;
  write(L,ret_string("Memory location 0020 (hex) contains the following: "));
  writeline(outfile,L);
  write(L,sccvar.m(32));
  writeline(outfile,L);
end scc;


procedure bsr is
begin
  null;
end;

procedure bcc is
begin
  null;
end;

procedure moveq is
begin
  null;
end;

procedure divu is
begin
  null;
end;

procedure divs is
begin
  null;
end;

procedure sbcd is
begin
  null;
end;
 
procedure orr is
begin
  null;
end;
 
procedure suba is
begin
  null;
end;
 
procedure subx is
begin
  null;
end;
 
procedure subb is
begin
  null;
end;
 
procedure cmp is
begin
  null;
end;
 
procedure cmpa is
begin
  null;
end;
 
procedure cmpm is
begin
  null;
end;
 
procedure eor is
begin
  null;
end;
 
procedure mulu is
begin
  null;
end;
 
procedure muls is
begin
  null;
end;
 
procedure abcd is
begin
  null;
end;
 
procedure exgd is
begin
  null;
end;
 
procedure exga is
begin
  null;
end;
 
procedure exgm is
begin
  null;
end;
 
procedure andd is
begin
  null;
end;
 
procedure adda is
begin
  null;
end;
 
procedure addx is
begin
  null;
end;
 
procedure add is
begin
  null;
end;
 
procedure asm is
begin
  null;
end;
 
procedure lsm is
begin
  null;
end;
 
procedure roxm is
begin
  null;
end;
 
procedure rom is
begin
  null;
end;
 
procedure asr is
begin
  null;
end;
 
procedure lsr is
begin
  null;
end;
 
procedure roxr is
begin
  null;
end;
 
procedure ror is
begin
  null;
end;
 
begin  --main loop
    var.m(0) := x"00";
    var.m(1) := x"00";
    var.m(2) := x"00";
    var.m(3) := x"FF";        -- set stack pointer to the top of memory
    var.m(4) := x"00";
    var.m(5) := x"00";
    var.m(6) := x"00";
    var.m(7) := x"08";          -- set initial PC = 8
    var.m(8) := x"4e";          -- jump
    var.m(9) := x"d1";
    var.m(10) := x"4e";         -- stop
    var.m(11) := x"72";
    var.m(12) := x"48";  	-- swap
    var.m(13) := x"42";
    var.m(14) := x"47";		-- lea
    var.m(15) := x"d1";
    var.m(16) := x"44";		-- move_to_ccr
    var.m(17) := x"d4";
    var.m(18) := x"54";		-- Scc
    var.m(19) := x"d5";
    var.m(20) := x"00";		-- ORI
    var.m(21) := x"95";
    var.m(22) := x"0f";
    var.m(23) := x"0f";
    var.m(24) := x"0f";
    var.m(25) := x"0f";
    var.m(26) := x"4e";         -- stop
    var.m(27) := x"72";
    var.areg(1) := x"0000000c";
    var.dreg(2) := x"12345678";
    var.areg(4) := x"00000009";
    var.areg(5) := x"00000020";
    var.prefetch := '1';
    var.sr := x"05c0";
    var.temp32(31 downto 24) := var.m(0);
    var.temp32(23 downto 16) := var.m(1);
    var.temp32(15 downto 8) := var.m(2);
    var.temp32(7 downto 0) := var.m(3);
    var.areg(7) := var.temp32;
    var.temp32(31 downto 24) := var.m(4);
    var.temp32(23 downto 16) := var.m(5);
    var.temp32(15 downto 8) := var.m(6);
    var.temp32(7 downto 0) := var.m(7);
    var.pc := var.temp32;
    var.dummy := bits_to_int(var.pc);
    var.temp16(15 downto 8) := var.m(var.dummy);
    var.dummy := var.dummy + 1;
    var.temp16(7 downto 0) := var.m(var.dummy);
    var.nir := var.temp16;
    loop
      instr_stream_fetch(var.nir, var.pc, var.prefetch, var.m, var.ir);
      case op_set is          --choose the proper type of execution
	when "0000" => 
	if (op_field_2a = '1') then
	  if (op_field_3 = "001") then movep;
	  else case op_field_2bc is
	  	 when "00" => btst_d;
	  	 when "01" => bchg_d;
	  	 when "10" => bclr_d;
	  	 when "11" => bset_d;
	       end case;
	  end if;
	else case op_field_1 is
		when "100" => case op_field_2bc is
				when "00" => btst_s;
				when "01" => bchg_s;
				when "10" => bclr_s;
				when "11" => bset_s;
			      end case;
		when "000" => if (var.ir(5 downto 0) = x"111100") then
				case size is
				  when "00" => ori_to_ccr;
				  when "01" => ori_to_sr;
				  when others =>n := '1';
				end case;
			      else ori(var);
			      end if;
		when "001" => if (var.ir(5 downto 0) = x"111100") then
				case size is
				  when "00" => andi_to_ccr;
				  when "01" => andi_to_sr;
				  when others =>n := '1';
				end case;
			      else andi;
			      end if;
		when "010" => subi;
		when "011" => addi;
		when "101" => if (var.ir(5 downto 0) = x"111100") then
				case size is
				  when "00" => eori_to_ccr;
				  when "01" => eori_to_sr;
				  when others =>n := '1';
				end case;
			      else eori;
			      end if;
		when "110" => cmpi;
		when others =>n := '1';
	     end case;
	end if;
	when "0001"|"0010"|"0011" => case op_set is
				       when "0010"|"0011" =>
				         if (op_field_2 = "001") then movea;
				         else move;
				         end if;
				       when others => move;
				     end case;
	when "0100" =>  var.dummy := bits_to_int(var.ir(11 downto 0));
			case var.dummy is
			  when 192  to 255  => move_from_sr;
			  when 0    to 191  => negx;
			  when 512  to 703  => clr;
			  when 1216 to 1279 => move_to_ccr(var);
			  when 1024 to 1215 => neg;
			  when 1728 to 1792 => move_to_sr;
			  when 1536 to 1727 => nott;
			  when 2048 to 2111 => nbcd;
			  when 2112 to 2119 => swap(var);
			  when 2120 to 2175 => pea;
			  when 2176 to 2183 => ext_w;
			  when 2240 to 2247 => ext_l;
			  when 2184 to 2239|2248 to 2303 => movem_rtoea;
			  when 2812 => illegal;
			  when 2752 to 2811 => tas;
			  when 2560 to 2751 => tst;
			  when 3200 to 3327 => movem_eator;
			  when 3655 to 3663 => trap;
			  when 3664 to 3671 => link;
			  when 3672 to 3679 => unlk;
			  when 3680 to 3687 => move_to_usp;
			  when 3688 to 3695 => move_from_usp;
			  when 3696 => reset;
			  when 3697 => nop;
			  when 3698 => stop;
			  when 3699 => rte;
			  when 3701 => rts;
			  when 3702 => trapv;
			  when 3703 => rtr;
			  when 3712 to 3775 => jsr;
			  when 3776 to 3839 => jmp(var);
			  when 384 to 447|896 to 959|1408 to 1471|
			       1920 to 1983|2432 to 2495|2944 to 3007|
			       3456 to 3519|3968 to 4031 => chk;
			  when 448 to 511|960 to 1023|1472 to 1535|
			       1984 to 2047|2496 to 2559|3008 to 3071|
			       3520 to 3583|4032 to 4095 => lea(var);
			  when others =>n := '1';
			end case;

	when "0101" => case op_field_2 is 
                        when "000" | "001" | "010" => addq;
			when "100" | "101" | "110" => subq;
			when "011" | "111" =>
			   if op_field_3 = "001" then dbcc;
                           else scc(var);
                           end if;
                       end case;
     
       when "0110" => if op_field_1 & op_field_2a = "0001" then bsr;
                   else bcc;
                   end if;
     
       when "0111" => moveq;

       when "1000" => var.dummy := bits_to_int(op_field_2 & op_field_3ab);
			case var.dummy is
                          when 12 to 15 => divu;
			  when 28 to 31 => divs;
			  when 16       => sbcd;
			  when others   => orr;
                   	end case;

      when "1001" => if op_field_2bc = "11" then suba;
                   else
		      if op_field_2a & op_field_3ab = "100" then subx;
                      else subb;
                      end if;
                   end if;
					  
      when "1011" => case op_field_2 is
		      when "000" | "001" | "010" => cmp;
		      when "011" | "111"         => cmpa;
		      when others => if op_field_3 = "001" then cmpm;
                                     else eor;
                                     end if;
                   end case;

      when "1100" => var.dummy := bits_to_int(op_field_2 & op_field_3);
                     case var.dummy is
			when 24 to 31 => mulu;
			when 56 to 63 => muls;
			when 32 to 33 => abcd;
			when 40       => exgd;
			when 41       => exga;
			when 49       => exgm;
			when others   => andd;
                     end case;
    
      when "1101" => if op_field_2bc = "11" then adda;
                     else
			if op_field_2a & op_field_3ab = "100" then addx;
                        else add;
                        end if;
                     end if;

      when "1110" => if op_field_2bc = "11" then
			case op_field_1 is
			  when "000" => asm;
			  when "001" => lsm;
			  when "010" => roxm;
			  when "011" => rom;
			  when others =>n := '1';
                        end case;
                     else
			case op_field_3bc is
			  when "00" => asr;
			  when "01" => lsr;
			  when "10" => roxr;
			  when "11" => ror;
                        end case;
                     end if;
      when others =>n := '1';
 end case;

	exception_check;
      end loop;
end process main;

end MC68000;