m68k.vhd

motorola m68k VHDL描述

               owvar.m(ow_int1) := ow_value(15 downto 8);
               ow_int1 := ow_int1 + 1;
               owvar.m(ow_int1) := ow_value(7 downto 0);
            when "10" =>
               addr_calc(owvar, ow_mode, ow_reg, ow_dummy);
               ow_int1 := bits_to_int(ow_dummy(7 downto 0));
               owvar.m(ow_int1) := ow_value(31 downto 24);
               ow_int1 := ow_int1 + 1;
               owvar.m(ow_int1) := ow_value(23 downto 16);
               ow_int1 := ow_int1 + 1;
               owvar.m(ow_int1) := ow_value(15 downto 8);
               ow_int1 := ow_int1 + 1;
               owvar.m(ow_int1) := ow_value(7 downto 0);
            when "11" => null;
         end case;
   end case;
end opr_write;

procedure movep is
begin
   null;
end movep;

procedure btst_d is
begin
   null;
end btst_d;

procedure bchg_d is
begin
   null;
end bchg_d;

procedure bclr_d is
begin
   null;
end bclr_d;

procedure bset_d is
begin
   null;
end bset_d;

procedure btst_s is
begin
   null;
end btst_s;

procedure bchg_s is
begin
   null;
end bchg_s;

procedure bclr_s is
begin
   null;
end bclr_s;

procedure bset_s is
begin
   null;
end bset_s;

procedure ori_to_ccr is
begin
   null;
end ori_to_ccr;

procedure ori_to_sr is
begin
   null;
end ori_to_sr;

function bitor(left, right: in bit_vector(31 downto 0)) return bit_vector is
   variable bittemp: bit_vector(31 downto 0);
begin
   for i in 0 to 31 loop
      bittemp(i) := left(i) or right(i);
   end loop;
   return bittemp;
end bitor;


procedure test(testvar: inout var_record; 
	       testsize: in bit_vector(1 downto 0);
	       testval: in bit_vector(31 downto 0)) is 
begin
   case testsize is
     when "00" => 
        testvar.nzvc(3) := testval(7);
        if (testval(7 downto 0) = x"00") then
          testvar.nzvc(2) := '1';
        else
          testvar.nzvc(2) := '0';
        end if;
     when "01" =>
        testvar.nzvc(3) := testval(15);
        if (testval(15 downto 0) = x"0000") then
          testvar.nzvc(2) := '1';
        else
          testvar.nzvc(2) := '0';
        end if;
     when "10" =>
        testvar.nzvc(3) := testval(31);
        if (testval(31 downto 0) = x"00000000") then
          testvar.nzvc(2) := '1';
        else
          testvar.nzvc(2) := '0';
        end if;
    when others => null;
  end case;
end test;

procedure ori(orvar: inout var_record) is
   variable ortemp1: bit_vector(31 downto 0);
   variable ortemp2: bit_vector(31 downto 0);
   variable ortemp3: bit_vector(31 downto 0);
begin
   write(L,ret_string("Entered ORI"));
   writeline(outfile,L);
   immediate(orvar.ir(7 downto 6), orvar.nir, orvar.pc, orvar.prefetch, orvar.m, ortemp2);
   opr_fetch(orvar,orvar.ir(7 downto 6),orvar.ir(5 downto 3),orvar.ir(2 downto 0),ortemp1);
   ortemp3 := bitor(ortemp1,ortemp2);
   opr_write(orvar,orvar.ir(7 downto 6),orvar.ir(5 downto 3),orvar.ir(2 downto 0),ortemp3);
   test(orvar, orvar.ir(7 downto 6), ortemp3);
   orvar.sr(11) := orvar.nzvc(3);
   orvar.sr(10) := orvar.nzvc(2);
   orvar.sr(9 downto 8) := "00";
   write(L,ret_string("Memory location 0020 (hex) contains the following: "));
   writeline(outfile,L);
   write(L,ret_string("   "));
   write(L,orvar.m(32));
   write(L,orvar.m(33));
   write(L,orvar.m(34));
   write(L,orvar.m(35));
   writeline(outfile,L);
end ori;

procedure andi_to_ccr is
begin
   null;
end andi_to_ccr;

procedure andi_to_sr is
begin
   null;
end andi_to_sr;

procedure andi is
begin
   null;
end andi;

procedure subi is
begin
   null;
end subi;

procedure addi is
begin
   null;
end addi;

procedure eori_to_ccr is
begin
   null;
end eori_to_ccr;

procedure eori_to_sr is
begin
   null;
end eori_to_sr;

procedure eori is
begin
   null;
end eori;

procedure cmpi is
begin
   null;
end cmpi;

procedure move is
begin
   null;
end move;

procedure movea is
begin
   null;
end movea;

procedure move_from_sr is
begin
   null;
end move_from_sr;

procedure negx is
begin
   null;
end negx;

procedure clr is
begin
   null;
end clr;

procedure move_to_ccr(mov_var: inout var_record) is
variable of_result :bit_vector(31 downto 0);
variable movesize :bit_vector(1 downto 0) := "01";
begin
        write(L,ret_string("Entering Move to CCR"));
        writeline(outfile,L);
        opr_fetch(mov_var,movesize,mov_var.ir(5 downto 3),mov_var.ir(2 downto 0),of_result);
        mov_var.sr(15 downto 8) := of_result(7 downto 0);
        write(L,ret_string("SR: "));
	write(L,mov_var.sr);
        writeline(outfile,L);
end move_to_ccr;

procedure neg is
begin
   null;
end neg;

procedure move_to_sr is
begin
   null;
end move_to_sr;

procedure nott is
begin
   null;
end nott;

procedure nbcd is
begin
   null;
end nbcd;

procedure swap(swvar: inout var_record) is
variable regno:integer;
begin
        write(L,ret_string("Entering Swap"));
        writeline(outfile,L);
        write(L,ret_string("Original register: "));
        write(L,swvar.dreg(2));
        writeline(outfile,L);
        regno := bits_to_int(swvar.ir(2 downto 0));
        write(L,regno);
        writeline(outfile,L);
        swvar.temp16 := swvar.dreg(regno)(15 downto 0);
        swvar.dreg(regno)(15 downto 0):= swvar.dreg(regno)(31 downto 16);
        swvar.dreg(regno)(31 downto 16):= swvar.temp16;
        write(L,ret_string("Swapped register: "));
        write(L,swvar.dreg(2));
        writeline(outfile,L); 
end swap;

procedure pea is
begin
   null;
end pea;

procedure ext_w is
begin
   null;
end ext_w;

procedure ext_l is
begin
   null;
end ext_l;

procedure movem_rtoea is
begin
   null;
end movem_rtoea;

procedure illegal is
begin
   null;
end illegal;

procedure tas is
begin
   null;
end tas;

procedure tst is
begin
   null;
end tst;

procedure movem_eator is
begin
   null;
end movem_eator;

procedure trap is
begin
   null;
end trap;

procedure link is
begin
   null;
end link;

procedure unlk is
begin
   null;
end unlk;

procedure move_to_usp is
begin
   null;
end move_to_usp;

procedure move_from_usp is
begin
   null;
end move_from_usp;

procedure reset is
begin
   null;
end reset;

procedure nop is
begin
   write(L,ret_string("Arrived at Nop instruction"));
   writeline(outfile,L);
   null;
end nop;

procedure stop is
begin
   write(L,ret_string("Arrived at Stop instruction"));
   writeline(outfile,L);
   wait;
end stop;

procedure rte is
begin
   null;
end rte;

procedure rts is
begin
   null;
end rts;

procedure trapv is
begin
   null;
end trapv;

procedure rtr is
begin
   null;
end rtr;

procedure jsr is
begin
   null;
end jsr;


procedure jmp(jmpvar: inout var_record) is
   variable addr :integer;
   variable acc_result :bit_vector(31 downto 0);

begin
        write(L,ret_string("Arrived at Jmp instruction"));
        writeline(outfile,L);
        jmpvar.prefetch := '0';
        addr_calc(jmpvar,jmpvar.ir(5 downto 3),jmpvar.ir(2 downto 0),acc_result);
        jmpvar.pc := acc_result;
        addr := bits_to_int(jmpvar.pc);
        jmpvar.nir(15 downto 8) := jmpvar.m(addr);
        jmpvar.nir(7 downto 0) := jmpvar.m(addr + 1);
        jmpvar.prefetch := '1';
end jmp;

procedure chk is
begin
   null;
end chk;

procedure lea(leavar:inout var_record) is
   variable acc_result: bit_vector(31 downto 0);
   variable regno: integer;
   variable temp: bit_vector(2 downto 0);
begin
   write(L,ret_string("Arrived at Lea instruction"));
   writeline(outfile,L);
   addr_calc(leavar,leavar.ir(5 downto 3),leavar.ir(2 downto 0),acc_result);
   temp := leavar.ir(11 downto 9);
   regno := bits_to_int(temp);
   leavar.areg(regno) := acc_result;
   write(L,ret_string("Areg(3): "));
   write(L,leavar.areg(3));
   writeline(outfile,L);
end lea;


procedure exception_check is
begin
   null;
end;

procedure addq is
begin
  null;
end;

procedure subq is
begin
  null;
end;

procedure dbcc is
begin
  null;
end;

procedure cc(ccvar :inout var_record;
             cond:in bit_vector(3 downto 0);
             res :out bit) is
variable condn :integer;
begin
        condn := bits_to_int(cond);
        case condn is
          when 0 => res := '1';
          when 1 => res := '0';
          when 2 => res := (not(ccvar.sr(8))) and (not(ccvar.sr(10)));