decl7s.map.summary

Quartus环境下的7段译码管的扫描显示电路

Analysis & Synthesis Status : Successful - Thu Nov 16 14:16:19 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : decl7s
Top-level Entity Name : DECL7S
Family : Cyclone
Total logic elements : 7
Total pins : 11
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0