📄 decl7s.tan.rpt
字号:
Timing Analyzer report for decl7s
Thu Nov 16 14:16:30 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.656 ns ; A[1] ; LED7S[1] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+---------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----------+
; N/A ; None ; 13.656 ns ; A[1] ; LED7S[1] ;
; N/A ; None ; 13.653 ns ; A[1] ; LED7S[0] ;
; N/A ; None ; 13.652 ns ; A[1] ; LED7S[5] ;
; N/A ; None ; 13.650 ns ; A[1] ; LED7S[6] ;
; N/A ; None ; 13.643 ns ; A[1] ; LED7S[4] ;
; N/A ; None ; 13.524 ns ; A[2] ; LED7S[5] ;
; N/A ; None ; 13.522 ns ; A[2] ; LED7S[6] ;
; N/A ; None ; 13.522 ns ; A[2] ; LED7S[0] ;
; N/A ; None ; 13.520 ns ; A[2] ; LED7S[1] ;
; N/A ; None ; 13.515 ns ; A[2] ; LED7S[4] ;
; N/A ; None ; 13.390 ns ; A[0] ; LED7S[1] ;
; N/A ; None ; 13.387 ns ; A[0] ; LED7S[0] ;
; N/A ; None ; 13.379 ns ; A[0] ; LED7S[5] ;
; N/A ; None ; 13.376 ns ; A[0] ; LED7S[4] ;
; N/A ; None ; 13.374 ns ; A[0] ; LED7S[6] ;
; N/A ; None ; 13.217 ns ; A[3] ; LED7S[1] ;
; N/A ; None ; 13.214 ns ; A[3] ; LED7S[0] ;
; N/A ; None ; 13.206 ns ; A[3] ; LED7S[5] ;
; N/A ; None ; 13.205 ns ; A[1] ; LED7S[2] ;
; N/A ; None ; 13.204 ns ; A[3] ; LED7S[4] ;
; N/A ; None ; 13.204 ns ; A[1] ; LED7S[3] ;
; N/A ; None ; 13.199 ns ; A[3] ; LED7S[6] ;
; N/A ; None ; 13.077 ns ; A[2] ; LED7S[2] ;
; N/A ; None ; 13.076 ns ; A[2] ; LED7S[3] ;
; N/A ; None ; 12.933 ns ; A[0] ; LED7S[3] ;
; N/A ; None ; 12.921 ns ; A[0] ; LED7S[2] ;
; N/A ; None ; 12.761 ns ; A[3] ; LED7S[3] ;
; N/A ; None ; 12.747 ns ; A[3] ; LED7S[2] ;
+-------+-------------------+-----------------+------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Thu Nov 16 14:16:30 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off decl7s -c decl7s --timing_analysis_only
Info: Longest tpd from source pin "A[1]" to destination pin "LED7S[1]" is 13.656 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_34; Fanout = 7; PIN Node = 'A[1]'
Info: 2: + IC(7.932 ns) + CELL(0.590 ns) = 9.991 ns; Loc. = LC_X26_Y9_N5; Fanout = 1; COMB Node = 'Mux~29'
Info: 3: + IC(1.541 ns) + CELL(2.124 ns) = 13.656 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'LED7S[1]'
Info: Total cell delay = 4.183 ns ( 30.63 % )
Info: Total interconnect delay = 9.473 ns ( 69.37 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Thu Nov 16 14:16:30 2006
Info: Elapsed time: 00:00:01
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -