singt.fit.eqn

Quartus环境下的正选信号发生器的实验源码

LB1L20 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[1], LB1L17);

--LB1L21 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~95COUT1_116 at LC_X11_Y7_N2
--operation mode is arithmetic

LB1L21 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[1], LB1L18);


--LB1_ram_rom_addr_reg[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2] at LC_X11_Y7_N3
--operation mode is arithmetic

LB1_ram_rom_addr_reg[2] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], !EB5_Q[0], LB1L10, LB1L20, LB1L21);

--LB1L23 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~99 at LC_X11_Y7_N3
--operation mode is arithmetic

LB1L23 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[2], LB1L20);

--LB1L24 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~99COUT1 at LC_X11_Y7_N3
--operation mode is arithmetic

LB1L24 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[2], LB1L21);


--LB1_ram_rom_addr_reg[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3] at LC_X11_Y7_N4
--operation mode is arithmetic

LB1_ram_rom_addr_reg[3] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], !EB5_Q[0], LB1L10, LB1L23, LB1L24);

--LB1L26 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~103 at LC_X11_Y7_N4
--operation mode is arithmetic

LB1L26 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[3], LB1L23, LB1L24);


--LB1_ram_rom_addr_reg[4] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4] at LC_X11_Y7_N5
--operation mode is arithmetic

LB1_ram_rom_addr_reg[4] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], !EB5_Q[0], LB1L10, LB1L26);

--LB1L30 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~107 at LC_X11_Y7_N5
--operation mode is arithmetic

LB1L30 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[4]);

--LB1L31 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~107COUT1_117 at LC_X11_Y7_N5
--operation mode is arithmetic

LB1L31 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[4]);


--LB1_ram_rom_addr_reg[5] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] at LC_X11_Y7_N6
--operation mode is normal

LB1_ram_rom_addr_reg[5] = AMPP_FUNCTION(A1L5, altera_internal_jtag, LB1_ram_rom_addr_reg[5], !EB5_Q[0], LB1L10, LB1L26, LB1L30, LB1L31);


--LB1_ram_rom_data_reg[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] at LC_X11_Y8_N9
--operation mode is normal

LB1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L5, LB1L11, KB1_q_b[1], LB1_ram_rom_data_reg[2], VCC, LB1L42);


--LB1_ram_rom_data_reg[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] at LC_X11_Y8_N5
--operation mode is normal

LB1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L5, LB1L11, KB1_q_b[2], LB1_ram_rom_data_reg[3], VCC, LB1L42);


--LB1_ram_rom_data_reg[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] at LC_X11_Y8_N6
--operation mode is normal

LB1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L5, KB1_q_b[3], LB1L11, LB1_ram_rom_data_reg[4], VCC, LB1L42);


--LB1_ram_rom_data_reg[4] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] at LC_X11_Y8_N2
--operation mode is normal

LB1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L5, LB1_ram_rom_data_reg[5], LB1L11, KB1_q_b[4], VCC, LB1L42);


--LB1_ram_rom_data_reg[5] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] at LC_X11_Y8_N7
--operation mode is normal

LB1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L5, LB1_ram_rom_data_reg[6], LB1L11, KB1_q_b[5], VCC, LB1L42);


--LB1_ram_rom_data_reg[6] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] at LC_X11_Y8_N8
--operation mode is normal

LB1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L5, LB1L11, KB1_q_b[6], LB1_ram_rom_data_reg[7], VCC, LB1L42);


--LB1_ram_rom_data_reg[7] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] at LC_X11_Y8_N0
--operation mode is normal

LB1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L5, KB1_q_b[7], LB1L11, altera_internal_jtag, VCC, LB1L42);


--C1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo at LC_X16_Y8_N7
--operation mode is normal

C1_hub_tdo = AMPP_FUNCTION(!A1L5, C1L19, C1L16, C1L13, C1L20, !GB1_state[8]);


--GB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] at LC_X16_Y8_N0
--operation mode is normal

GB1_state[4] = AMPP_FUNCTION(A1L5, GB1_state[3], GB1_state[4], GB1_state[7], VCC, A1L7);


--GB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] at LC_X10_Y8_N4
--operation mode is normal

GB1_state[3] = AMPP_FUNCTION(A1L5, A1L7, GB1_state[2], VCC);


--EB7_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2] at LC_X12_Y6_N2
--operation mode is normal

EB7_Q[2] = AMPP_FUNCTION(A1L5, EB3_Q[2], C1_CLRN_SIGNAL, C1L7);


--EB3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] at LC_X17_Y8_N7
--operation mode is normal

EB3_Q[2] = AMPP_FUNCTION(A1L5, C1L21, LB1_ir_loaded_address_reg[1], EB3_Q[3], H1L4, C1_CLRN_SIGNAL, GB1_state[4], EB3L4);


--C1_CLRN_SIGNAL is sld_hub:sld_hub_inst|CLRN_SIGNAL at LC_X10_Y7_N9
--operation mode is normal

C1_CLRN_SIGNAL = AMPP_FUNCTION(A1L5, EB1_Q[0], GB1_state[1], VCC);


--C1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q at LC_X12_Y9_N0
--operation mode is normal

C1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, GB1_state[8], C1_OK_TO_UPDATE_IR_Q, GB1_state[4], C1_jtag_debug_mode_usr1, VCC);


--C1L8 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~18 at LC_X16_Y7_N7
--operation mode is normal

C1L8 = AMPP_FUNCTION(GB1_state[5], C1_OK_TO_UPDATE_IR_Q);


--EB9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] at LC_X15_Y8_N5
--operation mode is normal

EB9_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, EB3_Q[8], VCC, C1L22);


--HB1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[2] at LC_X15_Y7_N6
--operation mode is normal

HB1_dffe1a[2] = AMPP_FUNCTION(A1L5, EB3_Q[1], EB3_Q[2], EB3_Q[3], C1L30, C1_CLRN_SIGNAL, C1L5);


--C1L23 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~124 at LC_X16_Y7_N2
--operation mode is normal

C1L23 = AMPP_FUNCTION(EB9_Q[0], HB1_dffe1a[2]);


--C1L24 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~125 at LC_X16_Y7_N4
--operation mode is normal

C1L24 = AMPP_FUNCTION(C1L8, EB8_Q[0], C1L23, EB2_Q[0]);


--C1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0 at LC_X15_Y7_N7
--operation mode is normal

C1_jtag_debug_mode_usr0 = AMPP_FUNCTION(A1L5, A1L43, L5_dffs[1], A1L44, L5_dffs[0], GB1_state[0], GB1_state[12]);


--C1L30 is sld_hub:sld_hub_inst|jtag_debug_mode~2 at LC_X15_Y7_N1
--operation mode is normal

C1L30 = AMPP_FUNCTION(C1_jtag_debug_mode_usr0, C1_jtag_debug_mode_usr1);


--GB1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] at LC_X10_Y8_N5
--operation mode is normal

GB1_state[12] = AMPP_FUNCTION(A1L5, GB1_state[10], GB1_state[11], VCC, !A1L7);


--GB1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] at LC_X10_Y8_N6
--operation mode is normal

GB1_state[2] = AMPP_FUNCTION(A1L5, GB1_state[15], GB1_state[8], GB1_state[1], VCC, !A1L7);


--C1L31 is sld_hub:sld_hub_inst|jtag_debug_mode~171 at LC_X10_Y8_N8
--operation mode is normal

C1L31 = AMPP_FUNCTION(GB1_state[2], A1L7, GB1_state[12]);


--GB1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] at LC_X10_Y8_N1
--operation mode is normal

GB1_state[15] = AMPP_FUNCTION(A1L5, GB1_state[12], GB1_state[14], VCC, !A1L7);


--GB1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] at LC_X10_Y8_N2
--operation mode is normal

GB1_state[0] = AMPP_FUNCTION(A1L5, GB1_state[0], GB1L19, A1L7, GB1_state[9], VCC);


--EB3_Q[8] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8] at LC_X17_Y5_N4
--operation mode is normal

EB3_Q[8] = AMPP_FUNCTION(A1L5, altera_internal_jtag, C1_CLRN_SIGNAL, GB1_state[4], C1L26);


--C1L22 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 at LC_X17_Y8_N1
--operation mode is normal

C1L22 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, GB1_state[4], A1L7, C1_OK_TO_UPDATE_IR_Q);


--L5_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] at LC_X15_Y8_N2
--operation mode is normal

L5_dffs[1] = AMPP_FUNCTION(A1L5, L5_dffs[2], GB1_state[0], GB1_state[11]);


--L5_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8] at LC_X15_Y8_N8
--operation mode is normal

L5_dffs[8] = AMPP_FUNCTION(A1L5, L5_dffs[9], GB1_state[0], GB1_state[11]);


--L5_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7] at LC_X15_Y8_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

L5_dffs[7] = AMPP_FUNCTION(A1L5, L5_dffs[8], GB1_state[0], GND, GB1_state[11]);


--L5_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6] at LC_X15_Y8_N7
--operation mode is normal