singt.tan.qmsg

Quartus环境下的正选信号发生器的实验源码

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DOUT\[6\] data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_address_reg0 12.985 ns memory " "Info: tco from clock \"CLK\" to destination pin \"DOUT\[6\]\" through memory \"data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_address_reg0\" is 12.985 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.792 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to source memory is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 29; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler"