singt.tan.qmsg

Quartus环境下的正选信号发生器的实验源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK1 register sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|regoutff register sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 116.59 MHz 8.577 ns Internal " "Info: Clock \"CLK1\" has Internal fmax of 116.59 MHz between source register \"sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|regoutff\" and destination register \"sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena\" (period= 8.577 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.354 ns + Longest register register " "Info: + Longest register to register delay is 8.354 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|regoutff 1 REG LC_X22_Y4_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y4_N4; Fanout = 1; REG Node = 'sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|regoutff'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" 369 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.605 ns) + CELL(0.590 ns) 2.195 ns sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~198 2 COMB LC_X18_Y7_N6 1 " "Info: 2: + IC(1.605 ns) + CELL(0.590 ns) = 2.195 ns; Loc. = LC_X18_Y7_N6; Fanout = 1; COMB Node = 'sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~198'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.195 ns" { sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~198 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 849 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.693 ns) + CELL(0.442 ns) 3.330 ns sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~200 3 COMB LC_X18_Y7_N2 2 " "Info: 3: + IC(0.693 ns) + CELL(0.442 ns) = 3.330 ns; Loc. = LC_X18_Y7_N2; Fanout = 2; COMB Node = 'sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~200'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "1.135 ns" { sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~198 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~200 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 849 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.590 ns) 4.371 ns sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~202 4 COMB LC_X18_Y7_N4 5 " "Info: 4: + IC(0.451 ns) + CELL(0.590 ns) = 4.371 ns; Loc. = LC_X18_Y7_N4; Fanout = 5; COMB Node = 'sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~202'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "1.041 ns" { sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~200 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~202 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 849 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.505 ns) + CELL(0.478 ns) 8.354 ns sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 5 REG LC_X21_Y8_N2 12 " "Info: 5: + IC(3.505 ns) + CELL(0.478 ns) = 8.354 ns; Loc. = LC_X21_Y8_N2; Fanout = 12; REG Node = 'sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "3.983 ns" { sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~202 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns ( 25.14 % ) " "Info: Total cell delay = 2.100 ns ( 25.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.254 ns ( 74.86 % ) " "Info: Total interconnect delay = 6.254 ns ( 74.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "8.354 ns" { sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~198 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~200 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~202 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.354 ns" { sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~198 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~200 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~202 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 1.605ns 0.693ns 0.451ns 3.505ns } { 0.000ns 0.590ns 0.442ns 0.590ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.038 ns - Smallest " "Info: - Smallest clock skew is 0.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 destination 2.781 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK1\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK1 1 CLK PIN_92 174 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 174; CLK Node = 'CLK1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { CLK1 } "NODE_NAME" } "" } } { "singt.vhd" "" { Text "E:/04003336 04003338/SINGT/singt.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 2 REG LC_X21_Y8_N2 12 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X21_Y8_N2; Fanout = 12; REG Node = 'sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "1.312 ns" { CLK1 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.781 ns" { CLK1 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK1 CLK1~out0 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 source 2.743 ns - Longest register " "Info: - Longest clock path from clock \"CLK1\" to source register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK1 1 CLK PIN_92 174 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 174; CLK Node = 'CLK1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { CLK1 } "NODE_NAME" } "" } } { "singt.vhd" "" { Text "E:/04003336 04003338/SINGT/singt.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|regoutff 2 REG LC_X22_Y4_N4 1 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X22_Y4_N4; Fanout = 1; REG Node = 'sld_signaltap:sinout\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|regoutff'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "1.274 ns" { CLK1 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" 369 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.743 ns" { CLK1 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.743 ns" { CLK1 CLK1~out0 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.781 ns" { CLK1 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK1 CLK1~out0 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.743 ns" { CLK1 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.743 ns" { CLK1 CLK1~out0 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" 369 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "8.354 ns" { sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~198 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~200 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~202 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.354 ns" { sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~198 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~200 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~202 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 1.605ns 0.693ns 0.451ns 3.505ns } { 0.000ns 0.590ns 0.442ns 0.590ns 0.478ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.781 ns" { CLK1 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK1 CLK1~out0 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.743 ns" { CLK1 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.743 ns" { CLK1 CLK1~out0 sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] altera_internal_jtag altera_internal_jtag~TCKUTAP 0.377 ns register " "Info: tsu for register \"sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 0.377 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.612 ns + Longest pin register " "Info: + Longest pin to register delay is 5.612 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y6_N1 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 13; PIN Node = 'altera_internal_jtag'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { altera_internal_jtag } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.362 ns) + CELL(0.292 ns) 2.654 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR~950 2 COMB LC_X17_Y8_N9 3 " "Info: 2: + IC(2.362 ns) + CELL(0.292 ns) = 2.654 ns; Loc. = LC_X17_Y8_N9; Fanout = 3; COMB Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR~950'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.654 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~950 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.220 ns) + CELL(0.738 ns) 5.612 ns sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] 3 REG LC_X19_Y6_N3 1 " "Info: 3: + IC(2.220 ns) + CELL(0.738 ns) = 5.612 ns; Loc. = LC_X19_Y6_N3; Fanout = 1; REG Node = 'sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.958 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~950 sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.030 ns ( 18.35 % ) " "Info: Total cell delay = 1.030 ns ( 18.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.582 ns ( 81.65 % ) " "Info: Total interconnect delay = 4.582 ns ( 81.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.612 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~950 sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.612 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~950 sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } { 0.000ns 2.362ns 2.220ns } { 0.000ns 0.292ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 299 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 299; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] 2 REG LC_X19_Y6_N3 1 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X19_Y6_N3; Fanout = 1; REG Node = 'sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.612 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~950 sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.612 ns" { altera_internal_jtag sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~950 sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } { 0.000ns 2.362ns 2.220ns } { 0.000ns 0.292ns 0.738ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}