singt.tan.qmsg

Quartus环境下的正选信号发生器的实验源码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK memory data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_datain_reg7 memory data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_memory_reg7 197.01 MHz 5.076 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 197.01 MHz between source memory \"data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_datain_reg7\" and destination memory \"data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_memory_reg7\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_datain_reg7 1 MEM M4K_X13_Y7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_datain_reg7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_71b2.tdf" "" { Text "E:/04003336 04003338/SINGT/db/altsyncram_71b2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_memory_reg7 2 MEM M4K_X13_Y7 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y7; Fanout = 0; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_memory_reg7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "4.319 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_71b2.tdf" "" { Text "E:/04003336 04003338/SINGT/db/altsyncram_71b2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "4.319 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.319 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.778 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 2.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 29; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { CLK } "NODE_NAME" } "" } } { "singt.vhd" "" { Text "E:/04003336 04003338/SINGT/singt.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.708 ns) 2.778 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_memory_reg7 2 MEM M4K_X13_Y7 0 " "Info: 2: + IC(0.601 ns) + CELL(0.708 ns) = 2.778 ns; Loc. = M4K_X13_Y7; Fanout = 0; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_memory_reg7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "1.309 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_71b2.tdf" "" { Text "E:/04003336 04003338/SINGT/db/altsyncram_71b2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 78.37 % ) " "Info: Total cell delay = 2.177 ns ( 78.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.63 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.778 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.778 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.792 ns - Longest memory " "Info: - Longest clock path from clock \"CLK\" to source memory is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 29; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { CLK } "NODE_NAME" } "" } } { "singt.vhd" "" { Text "E:/04003336 04003338/SINGT/singt.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.722 ns) 2.792 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_datain_reg7 2 MEM M4K_X13_Y7 1 " "Info: 2: + IC(0.601 ns) + CELL(0.722 ns) = 2.792 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_dcv:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a0~porta_datain_reg7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "1.323 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_71b2.tdf" "" { Text "E:/04003336 04003338/SINGT/db/altsyncram_71b2.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 78.47 % ) " "Info: Total cell delay = 2.191 ns ( 78.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.53 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.792 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.792 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.778 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.778 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.708ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.792 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.792 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_71b2.tdf" "" { Text "E:/04003336 04003338/SINGT/db/altsyncram_71b2.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_71b2.tdf" "" { Text "E:/04003336 04003338/SINGT/db/altsyncram_71b2.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "4.319 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.319 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.778 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.778 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.708ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.792 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.792 ns" { CLK CLK~out0 data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg7 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[5\] register sld_hub:sld_hub_inst\|hub_tdo 89.81 MHz 11.134 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 89.81 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[5\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 11.134 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.306 ns + Longest register register " "Info: + Longest register to register delay is 5.306 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[5\] 1 REG LC_X16_Y7_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y7_N8; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.590 ns) 1.784 ns sld_hub:sld_hub_inst\|hub_tdo~815 2 COMB LC_X19_Y7_N9 1 " "Info: 2: + IC(1.194 ns) + CELL(0.590 ns) = 1.784 ns; Loc. = LC_X19_Y7_N9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~815'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "1.784 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] sld_hub:sld_hub_inst|hub_tdo~815 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.055 ns) + CELL(0.292 ns) 4.131 ns sld_hub:sld_hub_inst\|hub_tdo~816 3 COMB LC_X16_Y8_N2 1 " "Info: 3: + IC(2.055 ns) + CELL(0.292 ns) = 4.131 ns; Loc. = LC_X16_Y8_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~816'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "2.347 ns" { sld_hub:sld_hub_inst|hub_tdo~815 sld_hub:sld_hub_inst|hub_tdo~816 } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.738 ns) 5.306 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X16_Y8_N7 1 " "Info: 4: + IC(0.437 ns) + CELL(0.738 ns) = 5.306 ns; Loc. = LC_X16_Y8_N7; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "1.175 ns" { sld_hub:sld_hub_inst|hub_tdo~816 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.620 ns ( 30.53 % ) " "Info: Total cell delay = 1.620 ns ( 30.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.686 ns ( 69.47 % ) " "Info: Total interconnect delay = 3.686 ns ( 69.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.306 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] sld_hub:sld_hub_inst|hub_tdo~815 sld_hub:sld_hub_inst|hub_tdo~816 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.306 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] sld_hub:sld_hub_inst|hub_tdo~815 sld_hub:sld_hub_inst|hub_tdo~816 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.194ns 2.055ns 0.437ns } { 0.000ns 0.590ns 0.292ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 299 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 299; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X16_Y8_N7 1 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X16_Y8_N7; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.272 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 299 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 299; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[5\] 2 REG LC_X16_Y7_N8 2 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X16_Y7_N8; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.306 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] sld_hub:sld_hub_inst|hub_tdo~815 sld_hub:sld_hub_inst|hub_tdo~816 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.306 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] sld_hub:sld_hub_inst|hub_tdo~815 sld_hub:sld_hub_inst|hub_tdo~816 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.194ns 2.055ns 0.437ns } { 0.000ns 0.590ns 0.292ns 0.738ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "singt" "UNKNOWN" "V1" "E:/04003336 04003338/SINGT/db/singt.quartus_db" { Floorplan "E:/04003336 04003338/SINGT/" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}