altsyncram_dcv.tdf

Quartus环境下的正选信号发生器的实验源码

--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" ENABLE_RUNTIME_MOD="YES" INIT_FILE="./dataHEX/SDATA.hex" INSTANCE_NAME="rom1" LOW_POWER_MODE="AUTO" NUMWORDS_A=64 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=6 address_a clock0 q_a
--VERSION_BEGIN 5.1 cbx_altsyncram 2005:10:21:05:19:54:SJ cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_compare 2005:07:12:04:41:28:SJ cbx_lpm_decode 2005:04:28:09:28:48:SJ cbx_lpm_mux 2005:04:28:09:25:00:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ  VERSION_END


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FUNCTION altsyncram_71b2 (address_a[5..0], address_b[5..0], clock0, clock1, data_b[7..0], wren_b)
RETURNS ( q_a[7..0], q_b[7..0]);
FUNCTION sld_mod_ram_rom (data_read[7..0])
WITH ( 	CVALUE,	IS_DATA_IN_RAM,	IS_READABLE,	NODE_NAME,	NUMWORDS,	SHIFT_COUNT_BITS,	WIDTH_WORD,	WIDTHAD) 
RETURNS ( address[5..0], data_write[7..0], enable_write, tck_usr);

--synthesis_resources = M4K 1 sld_mod_ram_rom 1 
SUBDESIGN altsyncram_dcv
( 
	address_a[5..0]	:	input;
	clock0	:	input;
	q_a[7..0]	:	output;
) 
VARIABLE 
	altsyncram1 : altsyncram_71b2;
	mgl_prim2 : sld_mod_ram_rom
		WITH (
			CVALUE = "00000000",
			IS_DATA_IN_RAM = 1,
			IS_READABLE = 1,
			NODE_NAME = 1919905073,
			NUMWORDS = 64,
			SHIFT_COUNT_BITS = 4,
			WIDTH_WORD = 8,
			WIDTHAD = 6
		);

BEGIN 
	altsyncram1.address_a[] = address_a[];
	altsyncram1.address_b[] = mgl_prim2.address[];
	altsyncram1.clock0 = clock0;
	altsyncram1.clock1 = mgl_prim2.tck_usr;
	altsyncram1.data_b[] = mgl_prim2.data_write[];
	altsyncram1.wren_b = mgl_prim2.enable_write;
	mgl_prim2.data_read[] = altsyncram1.q_b[];
	q_a[] = altsyncram1.q_a[];
END;
--VALID FILE