singt.map.eqn

Quartus环境下的正选信号发生器的实验源码

KB1_q_a[6] = KB1_q_a[6]_PORT_A_data_out[0];

--KB1_q_b[6] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[6]
KB1_q_b[6]_PORT_A_data_in = VCC;
KB1_q_b[6]_PORT_A_data_in_reg = DFFE(KB1_q_b[6]_PORT_A_data_in, KB1_q_b[6]_clock_0, , , );
KB1_q_b[6]_PORT_B_data_in = LB1_ram_rom_data_reg[6];
KB1_q_b[6]_PORT_B_data_in_reg = DFFE(KB1_q_b[6]_PORT_B_data_in, KB1_q_b[6]_clock_1, , , );
KB1_q_b[6]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[6]_PORT_A_address_reg = DFFE(KB1_q_b[6]_PORT_A_address, KB1_q_b[6]_clock_0, , , );
KB1_q_b[6]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[6]_PORT_B_address_reg = DFFE(KB1_q_b[6]_PORT_B_address, KB1_q_b[6]_clock_1, , , );
KB1_q_b[6]_PORT_A_write_enable = GND;
KB1_q_b[6]_PORT_A_write_enable_reg = DFFE(KB1_q_b[6]_PORT_A_write_enable, KB1_q_b[6]_clock_0, , , );
KB1_q_b[6]_PORT_B_write_enable = LB1L2;
KB1_q_b[6]_PORT_B_write_enable_reg = DFFE(KB1_q_b[6]_PORT_B_write_enable, KB1_q_b[6]_clock_1, , , );
KB1_q_b[6]_clock_0 = CLK;
KB1_q_b[6]_clock_1 = A1L5;
KB1_q_b[6]_PORT_B_data_out = MEMORY(KB1_q_b[6]_PORT_A_data_in_reg, KB1_q_b[6]_PORT_B_data_in_reg, KB1_q_b[6]_PORT_A_address_reg, KB1_q_b[6]_PORT_B_address_reg, KB1_q_b[6]_PORT_A_write_enable_reg, KB1_q_b[6]_PORT_B_write_enable_reg, , , KB1_q_b[6]_clock_0, KB1_q_b[6]_clock_1, , , , );
KB1_q_b[6] = KB1_q_b[6]_PORT_B_data_out[0];


--KB1_q_a[7] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[7]_PORT_A_data_in = VCC;
KB1_q_a[7]_PORT_A_data_in_reg = DFFE(KB1_q_a[7]_PORT_A_data_in, KB1_q_a[7]_clock_0, , , );
KB1_q_a[7]_PORT_B_data_in = LB1_ram_rom_data_reg[7];
KB1_q_a[7]_PORT_B_data_in_reg = DFFE(KB1_q_a[7]_PORT_B_data_in, KB1_q_a[7]_clock_1, , , );
KB1_q_a[7]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_a[7]_PORT_A_address_reg = DFFE(KB1_q_a[7]_PORT_A_address, KB1_q_a[7]_clock_0, , , );
KB1_q_a[7]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_a[7]_PORT_B_address_reg = DFFE(KB1_q_a[7]_PORT_B_address, KB1_q_a[7]_clock_1, , , );
KB1_q_a[7]_PORT_A_write_enable = GND;
KB1_q_a[7]_PORT_A_write_enable_reg = DFFE(KB1_q_a[7]_PORT_A_write_enable, KB1_q_a[7]_clock_0, , , );
KB1_q_a[7]_PORT_B_write_enable = LB1L2;
KB1_q_a[7]_PORT_B_write_enable_reg = DFFE(KB1_q_a[7]_PORT_B_write_enable, KB1_q_a[7]_clock_1, , , );
KB1_q_a[7]_clock_0 = CLK;
KB1_q_a[7]_clock_1 = A1L5;
KB1_q_a[7]_PORT_A_data_out = MEMORY(KB1_q_a[7]_PORT_A_data_in_reg, KB1_q_a[7]_PORT_B_data_in_reg, KB1_q_a[7]_PORT_A_address_reg, KB1_q_a[7]_PORT_B_address_reg, KB1_q_a[7]_PORT_A_write_enable_reg, KB1_q_a[7]_PORT_B_write_enable_reg, , , KB1_q_a[7]_clock_0, KB1_q_a[7]_clock_1, , , , );
KB1_q_a[7] = KB1_q_a[7]_PORT_A_data_out[0];

--KB1_q_b[7] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|q_b[7]
KB1_q_b[7]_PORT_A_data_in = VCC;
KB1_q_b[7]_PORT_A_data_in_reg = DFFE(KB1_q_b[7]_PORT_A_data_in, KB1_q_b[7]_clock_0, , , );
KB1_q_b[7]_PORT_B_data_in = LB1_ram_rom_data_reg[7];
KB1_q_b[7]_PORT_B_data_in_reg = DFFE(KB1_q_b[7]_PORT_B_data_in, KB1_q_b[7]_clock_1, , , );
KB1_q_b[7]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5]);
KB1_q_b[7]_PORT_A_address_reg = DFFE(KB1_q_b[7]_PORT_A_address, KB1_q_b[7]_clock_0, , , );
KB1_q_b[7]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5]);
KB1_q_b[7]_PORT_B_address_reg = DFFE(KB1_q_b[7]_PORT_B_address, KB1_q_b[7]_clock_1, , , );
KB1_q_b[7]_PORT_A_write_enable = GND;
KB1_q_b[7]_PORT_A_write_enable_reg = DFFE(KB1_q_b[7]_PORT_A_write_enable, KB1_q_b[7]_clock_0, , , );
KB1_q_b[7]_PORT_B_write_enable = LB1L2;
KB1_q_b[7]_PORT_B_write_enable_reg = DFFE(KB1_q_b[7]_PORT_B_write_enable, KB1_q_b[7]_clock_1, , , );
KB1_q_b[7]_clock_0 = CLK;
KB1_q_b[7]_clock_1 = A1L5;
KB1_q_b[7]_PORT_B_data_out = MEMORY(KB1_q_b[7]_PORT_A_data_in_reg, KB1_q_b[7]_PORT_B_data_in_reg, KB1_q_b[7]_PORT_A_address_reg, KB1_q_b[7]_PORT_B_address_reg, KB1_q_b[7]_PORT_A_write_enable_reg, KB1_q_b[7]_PORT_B_write_enable_reg, , , KB1_q_b[7]_clock_0, KB1_q_b[7]_clock_1, , , , );
KB1_q_b[7] = KB1_q_b[7]_PORT_B_data_out[0];


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);


--GB1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
--operation mode is normal

GB1_state[5] = AMPP_FUNCTION(A1L5, A1L7, GB1_state[4], GB1_state[3], VCC);


--EB5_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
--operation mode is normal

EB5_Q[2] = AMPP_FUNCTION(A1L5, EB7_Q[2], EB3_Q[2], EB2_Q[0], C1_CLRN_SIGNAL, C1L24);


--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
--operation mode is normal

C1_jtag_debug_mode = AMPP_FUNCTION(A1L5, C1L30, C1_jtag_debug_mode, C1L31, GB1_state[15], GB1_state[0]);


--EB8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal

EB8_Q[0] = AMPP_FUNCTION(A1L5, EB3_Q[8], altera_internal_jtag, C1_CLRN_SIGNAL, C1L22);


--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
--operation mode is normal

C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, L5_dffs[1], A1L37, A1L38, L5_dffs[0], GB1_state[0], GB1_state[12]);


--EB2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
--operation mode is normal

EB2_Q[0] = AMPP_FUNCTION(A1L5, HB1_dffe1a[1], EB2_Q[0], EB9_Q[0], C1L1, C1_CLRN_SIGNAL);


--LB1L47 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~21
--operation mode is normal

LB1L47 = AMPP_FUNCTION(C1_jtag_debug_mode, EB8_Q[0], C1_jtag_debug_mode_usr1, EB2_Q[0]);


--LB1L2 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11
--operation mode is normal

LB1L2 = AMPP_FUNCTION(GB1_state[5], EB5_Q[2], LB1L47);


--Q1[0] is Q1[0]
--operation mode is arithmetic

Q1[0]_lut_out = !Q1[0];
Q1[0] = DFFEAS(Q1[0]_lut_out, CLK, VCC, , , , , , );

--A1L27 is Q1[0]~43
--operation mode is arithmetic

A1L27 = CARRY(Q1[0]);


--Q1[1] is Q1[1]
--operation mode is arithmetic

Q1[1]_carry_eqn = A1L27;
Q1[1]_lut_out = Q1[1] $ (Q1[1]_carry_eqn);
Q1[1] = DFFEAS(Q1[1]_lut_out, CLK, VCC, , , , , , );

--A1L29 is Q1[1]~47
--operation mode is arithmetic

A1L29 = CARRY(!A1L27 # !Q1[1]);


--Q1[2] is Q1[2]
--operation mode is arithmetic

Q1[2]_carry_eqn = A1L29;
Q1[2]_lut_out = Q1[2] $ (!Q1[2]_carry_eqn);
Q1[2] = DFFEAS(Q1[2]_lut_out, CLK, VCC, , , , , , );

--A1L31 is Q1[2]~51
--operation mode is arithmetic

A1L31 = CARRY(Q1[2] & (!A1L29));


--Q1[3] is Q1[3]
--operation mode is arithmetic

Q1[3]_carry_eqn = A1L31;
Q1[3]_lut_out = Q1[3] $ (Q1[3]_carry_eqn);
Q1[3] = DFFEAS(Q1[3]_lut_out, CLK, VCC, , , , , , );

--A1L33 is Q1[3]~55
--operation mode is arithmetic

A1L33 = CARRY(!A1L31 # !Q1[3]);


--Q1[4] is Q1[4]
--operation mode is arithmetic

Q1[4]_carry_eqn = A1L33;
Q1[4]_lut_out = Q1[4] $ (!Q1[4]_carry_eqn);
Q1[4] = DFFEAS(Q1[4]_lut_out, CLK, VCC, , , , , , );

--A1L35 is Q1[4]~59
--operation mode is arithmetic

A1L35 = CARRY(Q1[4] & (!A1L33));


--Q1[5] is Q1[5]
--operation mode is normal

Q1[5]_carry_eqn = A1L35;
Q1[5]_lut_out = Q1[5] $ (Q1[5]_carry_eqn);
Q1[5] = DFFEAS(Q1[5]_lut_out, CLK, VCC, , , , , , );


--LB1_ram_rom_data_reg[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
--operation mode is normal

LB1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L5, KB1_q_b[0], LB1_ram_rom_data_reg[1], LB1L11, VCC, LB1L36);


--LB1_ram_rom_addr_reg[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]
--operation mode is arithmetic

LB1_ram_rom_addr_reg[0] = AMPP_FUNCTION(A1L5, LB1_ram_rom_incr_addr, LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], !EB5_Q[0], LB1L10);

--LB1L17 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~91
--operation mode is arithmetic

LB1L17 = AMPP_FUNCTION(LB1_ram_rom_incr_addr, LB1_ram_rom_addr_reg[0]);


--LB1_ram_rom_addr_reg[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]
--operation mode is arithmetic

LB1_ram_rom_addr_reg[1] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], !EB5_Q[0], LB1L10, LB1L17);

--LB1L19 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~95
--operation mode is arithmetic

LB1L19 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[1], LB1L17);


--LB1_ram_rom_addr_reg[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]
--operation mode is arithmetic

LB1_ram_rom_addr_reg[2] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], !EB5_Q[0], LB1L10, LB1L19);

--LB1L21 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~99
--operation mode is arithmetic

LB1L21 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[2], LB1L19);


--LB1_ram_rom_addr_reg[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]
--operation mode is arithmetic

LB1_ram_rom_addr_reg[3] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], !EB5_Q[0], LB1L10, LB1L21);

--LB1L23 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~103
--operation mode is arithmetic

LB1L23 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[3], LB1L21);


--LB1_ram_rom_addr_reg[4] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]
--operation mode is arithmetic

LB1_ram_rom_addr_reg[4] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], !EB5_Q[0], LB1L10, LB1L23);

--LB1L25 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~107
--operation mode is arithmetic

LB1L25 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[4], LB1L23);


--LB1_ram_rom_addr_reg[5] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]
--operation mode is normal

LB1_ram_rom_addr_reg[5] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[5], altera_internal_jtag, !EB5_Q[0], LB1L10, LB1L25);


--LB1_ram_rom_data_reg[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]
--operation mode is normal

LB1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L5, KB1_q_b[1], LB1_ram_rom_data_reg[2], LB1L11, VCC, LB1L36);


--LB1_ram_rom_data_reg[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]
--operation mode is normal

LB1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L5, KB1_q_b[2], LB1_ram_rom_data_reg[3], LB1L11, VCC, LB1L36);


--LB1_ram_rom_data_reg[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]
--operation mode is normal

LB1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L5, KB1_q_b[3], LB1_ram_rom_data_reg[4], LB1L11, VCC, LB1L36);