stp1.stp

Quartus环境下的正选信号发生器的实验源码

<session jtag_chain="ByteBlasterII [LPT1]" jtag_device="@1: EP1C3 (0x020810DD)" sof_file="singt.sof">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="sinout" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="sinout" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="3"/>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2006/11/28 16:01:55  #0">
      <clock name="CLK1" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="no" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="DOUT[0]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[1]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[2]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[3]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[4]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[5]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[6]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[7]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="Q1[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[5]" tap_mode="classic" type="register"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire connection_status="true" name="DOUT[0]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[1]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[2]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[3]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[4]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[5]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[6]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="DOUT[7]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="Q1[0]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[1]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[2]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[3]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[4]" tap_mode="classic" type="register"/>
          <wire connection_status="true" name="Q1[5]" tap_mode="classic" type="register"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <setup_view>
          <bus is_signal_inverted="no" link="all" name="DOUT" order="msb_to_lsb" radix="line" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="DOUT[7]"/>
            <net is_signal_inverted="no" name="DOUT[6]"/>
            <net is_signal_inverted="no" name="DOUT[5]"/>
            <net is_signal_inverted="no" name="DOUT[4]"/>
            <net is_signal_inverted="no" name="DOUT[3]"/>
            <net is_signal_inverted="no" name="DOUT[2]"/>
            <net is_signal_inverted="no" name="DOUT[1]"/>
            <net is_signal_inverted="no" name="DOUT[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="Q1" order="msb_to_lsb" radix="line" state="collapse" type="register">
            <net is_signal_inverted="no" name="Q1[5]"/>
            <net is_signal_inverted="no" name="Q1[4]"/>
            <net is_signal_inverted="no" name="Q1[3]"/>