singt.tan.rpt

Quartus环境下的正选信号发生器的实验源码

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                                                                                                  ; To                                                                                                                                         ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 0.377 ns                         ; altera_internal_jtag                                                                                                                                                                                                                                  ; sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3]                                                                                      ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 12.985 ns                        ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_address_reg5                                                                                                                 ; DOUT[6]                                                                                                                                    ; CLK                          ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                                                                                              ; altera_reserved_tdo                                                                                                                        ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.661 ns                         ; altera_internal_jtag                                                                                                                                                                                                                                  ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                    ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 89.81 MHz ( period = 11.134 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5]                                                                                                                                                                                                    ; sld_hub:sld_hub_inst|hub_tdo                                                                                                               ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLK1'                         ; N/A   ; None          ; 116.59 MHz ( period = 8.577 ns ) ; sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|regoutff ; sld_signaltap:sinout|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ; CLK1                         ; CLK1                         ; 0            ;
; Clock Setup: 'CLK'                          ; N/A   ; None          ; 197.01 MHz ( period = 5.076 ns ) ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_datain_reg0                                                                                                                  ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_dcv:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a0~porta_memory_reg0       ; CLK                          ; CLK                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                                                                                                       ;                                                                                                                                            ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;