data_rom.vhd

Quartus环境下的正选信号发生器的实验源码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY data_rom IS
PORT( address : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );
END data_rom;
ARCHITECTURE SYN OF data_rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC ( intended_device_family : STRING;
width_a, widthad_a,numwords_a : NATURAL;
operation_mode : STRING;
outdata_reg_a,address_aclr_a, outdata_aclr_a : STRING;
width_byteena_a : NATURAL;
init_file, lpm_hint, lpm_type : STRING );
PORT ( clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (intended_device_family => "Cyclone",
width_a => 8, widthad_a => 6, numwords_a => 64,
operation_mode => "ROM",
outdata_reg_a => "UNREGISTERED",
address_aclr_a => "NONE", outdata_aclr_a => "NONE",
width_byteena_a => 1,
init_file => "./dataHEX/SDATA.hex",
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=rom1",
lpm_type => "altsyncram" )
PORT MAP (clock0 => inclock,address_a => address, q_a => sub_wire0);
END SYN;