cntshow.tan.qmsg

Quartus环境下的12进制计数器的扫描显示电路

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register CNT12:u1\|CQI\[3\] CNT12:u1\|CQI\[2\] 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"CNT12:u1\|CQI\[3\]\" and destination register \"CNT12:u1\|CQI\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.462 ns + Longest register register " "Info: + Longest register to register delay is 1.462 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT12:u1\|CQI\[3\] 1 REG LC_X26_Y10_N2 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N2; Fanout = 12; REG Node = 'CNT12:u1\|CQI\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "" { CNT12:u1|CQI[3] } "NODE_NAME" } "" } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.738 ns) 1.462 ns CNT12:u1\|CQI\[2\] 2 REG LC_X26_Y10_N5 12 " "Info: 2: + IC(0.724 ns) + CELL(0.738 ns) = 1.462 ns; Loc. = LC_X26_Y10_N5; Fanout = 12; REG Node = 'CNT12:u1\|CQI\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "1.462 ns" { CNT12:u1|CQI[3] CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 50.48 % ) " "Info: Total cell delay = 0.738 ns ( 50.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.724 ns ( 49.52 % ) " "Info: Total interconnect delay = 0.724 ns ( 49.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "1.462 ns" { CNT12:u1|CQI[3] CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.462 ns" { CNT12:u1|CQI[3] CNT12:u1|CQI[2] } { 0.000ns 0.724ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.781 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "" { CLK } "NODE_NAME" } "" } } { "cntshow.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns CNT12:u1\|CQI\[2\] 2 REG LC_X26_Y10_N5 12 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y10_N5; Fanout = 12; REG Node = 'CNT12:u1\|CQI\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "1.312 ns" { CLK CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.781 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "" { CLK } "NODE_NAME" } "" } } { "cntshow.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns CNT12:u1\|CQI\[3\] 2 REG LC_X26_Y10_N2 12 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y10_N2; Fanout = 12; REG Node = 'CNT12:u1\|CQI\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "1.312 ns" { CLK CNT12:u1|CQI[3] } "NODE_NAME" } "" } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[3] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[3] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "1.462 ns" { CNT12:u1|CQI[3] CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.462 ns" { CNT12:u1|CQI[3] CNT12:u1|CQI[2] } { 0.000ns 0.724ns } { 0.000ns 0.738ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[3] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "" { CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { CNT12:u1|CQI[2] } {  } {  } } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "CNT12:u1\|CQI\[0\] EN CLK 7.053 ns register " "Info: tsu for register \"CNT12:u1\|CQI\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is 7.053 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.797 ns + Longest pin register " "Info: + Longest pin to register delay is 9.797 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns EN 1 PIN PIN_11 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 4; PIN Node = 'EN'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "" { EN } "NODE_NAME" } "" } } { "cntshow.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.461 ns) + CELL(0.867 ns) 9.797 ns CNT12:u1\|CQI\[0\] 2 REG LC_X26_Y10_N7 12 " "Info: 2: + IC(7.461 ns) + CELL(0.867 ns) = 9.797 ns; Loc. = LC_X26_Y10_N7; Fanout = 12; REG Node = 'CNT12:u1\|CQI\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "8.328 ns" { EN CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 23.84 % ) " "Info: Total cell delay = 2.336 ns ( 23.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.461 ns ( 76.16 % ) " "Info: Total interconnect delay = 7.461 ns ( 76.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "9.797 ns" { EN CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.797 ns" { EN EN~out0 CNT12:u1|CQI[0] } { 0.000ns 0.000ns 7.461ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.781 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "" { CLK } "NODE_NAME" } "" } } { "cntshow.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns CNT12:u1\|CQI\[0\] 2 REG LC_X26_Y10_N7 12 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y10_N7; Fanout = 12; REG Node = 'CNT12:u1\|CQI\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "1.312 ns" { CLK CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[0] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "9.797 ns" { EN CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.797 ns" { EN EN~out0 CNT12:u1|CQI[0] } { 0.000ns 0.000ns 7.461ns } { 0.000ns 1.469ns 0.867ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[0] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK COUT CNT12:u1\|CQI\[2\] 9.318 ns register " "Info: tco from clock \"CLK\" to destination pin \"COUT\" through register \"CNT12:u1\|CQI\[2\]\" is 9.318 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.781 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "" { CLK } "NODE_NAME" } "" } } { "cntshow.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns CNT12:u1\|CQI\[2\] 2 REG LC_X26_Y10_N5 12 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y10_N5; Fanout = 12; REG Node = 'CNT12:u1\|CQI\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "1.312 ns" { CLK CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.313 ns + Longest register pin " "Info: + Longest register to pin delay is 6.313 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT12:u1\|CQI\[2\] 1 REG LC_X26_Y10_N5 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N5; Fanout = 12; REG Node = 'CNT12:u1\|CQI\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "" { CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.307 ns) + CELL(0.590 ns) 1.897 ns rtl~20 2 COMB LC_X26_Y11_N4 1 " "Info: 2: + IC(1.307 ns) + CELL(0.590 ns) = 1.897 ns; Loc. = LC_X26_Y11_N4; Fanout = 1; COMB Node = 'rtl~20'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "1.897 ns" { CNT12:u1|CQI[2] rtl~20 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.308 ns) + CELL(2.108 ns) 6.313 ns COUT 3 PIN PIN_123 0 " "Info: 3: + IC(2.308 ns) + CELL(2.108 ns) = 6.313 ns; Loc. = PIN_123; Fanout = 0; PIN Node = 'COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "4.416 ns" { rtl~20 COUT } "NODE_NAME" } "" } } { "cntshow.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.698 ns ( 42.74 % ) " "Info: Total cell delay = 2.698 ns ( 42.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.615 ns ( 57.26 % ) " "Info: Total interconnect delay = 3.615 ns ( 57.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "6.313 ns" { CNT12:u1|CQI[2] rtl~20 COUT } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.313 ns" { CNT12:u1|CQI[2] rtl~20 COUT } { 0.000ns 1.307ns 2.308ns } { 0.000ns 0.590ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "6.313 ns" { CNT12:u1|CQI[2] rtl~20 COUT } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.313 ns" { CNT12:u1|CQI[2] rtl~20 COUT } { 0.000ns 1.307ns 2.308ns } { 0.000ns 0.590ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "CNT12:u1\|CQI\[0\] EN CLK -7.001 ns register " "Info: th for register \"CNT12:u1\|CQI\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is -7.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.781 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "" { CLK } "NODE_NAME" } "" } } { "cntshow.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns CNT12:u1\|CQI\[0\] 2 REG LC_X26_Y10_N7 12 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y10_N7; Fanout = 12; REG Node = 'CNT12:u1\|CQI\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "1.312 ns" { CLK CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[0] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.797 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.797 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns EN 1 PIN PIN_11 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 4; PIN Node = 'EN'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "" { EN } "NODE_NAME" } "" } } { "cntshow.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.461 ns) + CELL(0.867 ns) 9.797 ns CNT12:u1\|CQI\[0\] 2 REG LC_X26_Y10_N7 12 " "Info: 2: + IC(7.461 ns) + CELL(0.867 ns) = 9.797 ns; Loc. = LC_X26_Y10_N7; Fanout = 12; REG Node = 'CNT12:u1\|CQI\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "8.328 ns" { EN CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 23.84 % ) " "Info: Total cell delay = 2.336 ns ( 23.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.461 ns ( 76.16 % ) " "Info: Total interconnect delay = 7.461 ns ( 76.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "9.797 ns" { EN CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.797 ns" { EN EN~out0 CNT12:u1|CQI[0] } { 0.000ns 0.000ns 7.461ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "2.781 ns" { CLK CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT12:u1|CQI[0] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cntshow" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/db/cntshow.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/" "" "9.797 ns" { EN CNT12:u1|CQI[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.797 ns" { EN EN~out0 CNT12:u1|CQI[0] } { 0.000ns 0.000ns 7.461ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}