cntshow.map.qmsg

Quartus环境下的12进制计数器的扫描显示电路

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 17 17:11:28 2006 " "Info: Processing started: Fri Nov 17 17:11:28 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cntshow -c cntshow " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cntshow -c cntshow" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/04003336 04003338/cntshow/cnt12.vhd " "Warning: Can't analyze file -- file E:/04003336 04003338/cntshow/cnt12.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decl7s.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decl7s.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DECL7S-one " "Info: Found design unit 1: DECL7S-one" {  } { { "decl7s.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/decl7s.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DECL7S " "Info: Found entity 1: DECL7S" {  } { { "decl7s.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/decl7s.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cntshow.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cntshow.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cntshow-arch " "Info: Found design unit 1: cntshow-arch" {  } { { "cntshow.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cntshow " "Info: Found entity 1: cntshow" {  } { { "cntshow.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cntshow " "Info: Elaborating entity \"cntshow\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cnt12.vhd 2 1 " "Warning: Using design file cnt12.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT12-behav " "Info: Found design unit 1: CNT12-behav" {  } { { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT12 " "Info: Found entity 1: CNT12" {  } { { "cnt12.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cnt12.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt12 cnt12:u1 " "Info: Elaborating entity \"cnt12\" for hierarchy \"cnt12:u1\"" {  } { { "cntshow.vhd" "u1" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 26 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DECL7S DECL7S:u2 " "Info: Elaborating entity \"DECL7S\" for hierarchy \"DECL7S:u2\"" {  } { { "cntshow.vhd" "u2" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/cntshow.vhd" 27 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "decl7s.vhd(28) " "Info (10425): VHDL Case Statement information at decl7s.vhd(28): OTHERS choice is never selected" {  } { { "decl7s.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/cntshow/decl7s.vhd" 28 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "23 " "Info: Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "12 " "Info: Implemented 12 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 17 17:11:31 2006 " "Info: Processing ended: Fri Nov 17 17:11:31 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}