cntshow.tan.rpt

Quartus环境下的12进制计数器的扫描显示电路

+-------+--------------+------------+-----------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To       ; From Clock ;
+-------+--------------+------------+-----------------+----------+------------+
; N/A   ; None         ; 9.318 ns   ; CNT12:u1|CQI[2] ; COUT     ; CLK        ;
; N/A   ; None         ; 9.121 ns   ; CNT12:u1|CQI[0] ; COUT     ; CLK        ;
; N/A   ; None         ; 9.017 ns   ; CNT12:u1|CQI[3] ; COUT     ; CLK        ;
; N/A   ; None         ; 8.811 ns   ; CNT12:u1|CQI[1] ; COUT     ; CLK        ;
; N/A   ; None         ; 8.507 ns   ; CNT12:u1|CQI[2] ; LED7S[6] ; CLK        ;
; N/A   ; None         ; 8.312 ns   ; CNT12:u1|CQI[0] ; LED7S[6] ; CLK        ;
; N/A   ; None         ; 8.208 ns   ; CNT12:u1|CQI[3] ; LED7S[6] ; CLK        ;
; N/A   ; None         ; 8.001 ns   ; CNT12:u1|CQI[1] ; LED7S[6] ; CLK        ;
; N/A   ; None         ; 7.990 ns   ; CNT12:u1|CQI[3] ; LED7S[1] ; CLK        ;
; N/A   ; None         ; 7.974 ns   ; CNT12:u1|CQI[3] ; LED7S[0] ; CLK        ;
; N/A   ; None         ; 7.966 ns   ; CNT12:u1|CQI[3] ; LED7S[2] ; CLK        ;
; N/A   ; None         ; 7.961 ns   ; CNT12:u1|CQI[3] ; LED7S[3] ; CLK        ;
; N/A   ; None         ; 7.959 ns   ; CNT12:u1|CQI[3] ; LED7S[5] ; CLK        ;
; N/A   ; None         ; 7.806 ns   ; CNT12:u1|CQI[1] ; LED7S[1] ; CLK        ;
; N/A   ; None         ; 7.787 ns   ; CNT12:u1|CQI[1] ; LED7S[0] ; CLK        ;
; N/A   ; None         ; 7.781 ns   ; CNT12:u1|CQI[1] ; LED7S[2] ; CLK        ;
; N/A   ; None         ; 7.777 ns   ; CNT12:u1|CQI[1] ; LED7S[3] ; CLK        ;
; N/A   ; None         ; 7.770 ns   ; CNT12:u1|CQI[1] ; LED7S[5] ; CLK        ;
; N/A   ; None         ; 7.706 ns   ; CNT12:u1|CQI[0] ; LED7S[1] ; CLK        ;
; N/A   ; None         ; 7.687 ns   ; CNT12:u1|CQI[0] ; LED7S[5] ; CLK        ;
; N/A   ; None         ; 7.684 ns   ; CNT12:u1|CQI[0] ; LED7S[3] ; CLK        ;
; N/A   ; None         ; 7.676 ns   ; CNT12:u1|CQI[0] ; LED7S[2] ; CLK        ;
; N/A   ; None         ; 7.669 ns   ; CNT12:u1|CQI[0] ; LED7S[0] ; CLK        ;
; N/A   ; None         ; 7.551 ns   ; CNT12:u1|CQI[2] ; LED7S[1] ; CLK        ;
; N/A   ; None         ; 7.534 ns   ; CNT12:u1|CQI[2] ; LED7S[5] ; CLK        ;
; N/A   ; None         ; 7.529 ns   ; CNT12:u1|CQI[2] ; LED7S[3] ; CLK        ;
; N/A   ; None         ; 7.527 ns   ; CNT12:u1|CQI[3] ; LED7S[4] ; CLK        ;
; N/A   ; None         ; 7.520 ns   ; CNT12:u1|CQI[2] ; LED7S[2] ; CLK        ;
; N/A   ; None         ; 7.508 ns   ; CNT12:u1|CQI[2] ; LED7S[0] ; CLK        ;
; N/A   ; None         ; 7.341 ns   ; CNT12:u1|CQI[1] ; LED7S[4] ; CLK        ;
; N/A   ; None         ; 7.230 ns   ; CNT12:u1|CQI[0] ; LED7S[4] ; CLK        ;
; N/A   ; None         ; 7.074 ns   ; CNT12:u1|CQI[2] ; LED7S[4] ; CLK        ;
+-------+--------------+------------+-----------------+----------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To              ; To Clock ;
+---------------+-------------+-----------+------+-----------------+----------+
; N/A           ; None        ; -7.001 ns ; EN   ; CNT12:u1|CQI[0] ; CLK      ;
; N/A           ; None        ; -7.001 ns ; EN   ; CNT12:u1|CQI[2] ; CLK      ;
; N/A           ; None        ; -7.001 ns ; EN   ; CNT12:u1|CQI[3] ; CLK      ;
; N/A           ; None        ; -7.001 ns ; EN   ; CNT12:u1|CQI[1] ; CLK      ;
+---------------+-------------+-----------+------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Nov 17 17:11:44 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cntshow -c cntshow --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "CNT12:u1|CQI[3]" and destination register "CNT12:u1|CQI[2]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.462 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N2; Fanout = 12; REG Node = 'CNT12:u1|CQI[3]'
            Info: 2: + IC(0.724 ns) + CELL(0.738 ns) = 1.462 ns; Loc. = LC_X26_Y10_N5; Fanout = 12; REG Node = 'CNT12:u1|CQI[2]'
            Info: Total cell delay = 0.738 ns ( 50.48 % )
            Info: Total interconnect delay = 0.724 ns ( 49.52 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.781 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y10_N5; Fanout = 12; REG Node = 'CNT12:u1|CQI[2]'
                Info: Total cell delay = 2.180 ns ( 78.39 % )
                Info: Total interconnect delay = 0.601 ns ( 21.61 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.781 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y10_N2; Fanout = 12; REG Node = 'CNT12:u1|CQI[3]'
                Info: Total cell delay = 2.180 ns ( 78.39 % )
                Info: Total interconnect delay = 0.601 ns ( 21.61 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "CNT12:u1|CQI[0]" (data pin = "EN", clock pin = "CLK") is 7.053 ns
    Info: + Longest pin to register delay is 9.797 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 4; PIN Node = 'EN'
        Info: 2: + IC(7.461 ns) + CELL(0.867 ns) = 9.797 ns; Loc. = LC_X26_Y10_N7; Fanout = 12; REG Node = 'CNT12:u1|CQI[0]'
        Info: Total cell delay = 2.336 ns ( 23.84 % )
        Info: Total interconnect delay = 7.461 ns ( 76.16 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y10_N7; Fanout = 12; REG Node = 'CNT12:u1|CQI[0]'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
Info: tco from clock "CLK" to destination pin "COUT" through register "CNT12:u1|CQI[2]" is 9.318 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y10_N5; Fanout = 12; REG Node = 'CNT12:u1|CQI[2]'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.313 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N5; Fanout = 12; REG Node = 'CNT12:u1|CQI[2]'
        Info: 2: + IC(1.307 ns) + CELL(0.590 ns) = 1.897 ns; Loc. = LC_X26_Y11_N4; Fanout = 1; COMB Node = 'rtl~20'
        Info: 3: + IC(2.308 ns) + CELL(2.108 ns) = 6.313 ns; Loc. = PIN_123; Fanout = 0; PIN Node = 'COUT'
        Info: Total cell delay = 2.698 ns ( 42.74 % )
        Info: Total interconnect delay = 3.615 ns ( 57.26 % )
Info: th for register "CNT12:u1|CQI[0]" (data pin = "EN", clock pin = "CLK") is -7.001 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y10_N7; Fanout = 12; REG Node = 'CNT12:u1|CQI[0]'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 9.797 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 4; PIN Node = 'EN'
        Info: 2: + IC(7.461 ns) + CELL(0.867 ns) = 9.797 ns; Loc. = LC_X26_Y10_N7; Fanout = 12; REG Node = 'CNT12:u1|CQI[0]'
        Info: Total cell delay = 2.336 ns ( 23.84 % )
        Info: Total interconnect delay = 7.461 ns ( 76.16 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Nov 17 17:11:44 2006
    Info: Elapsed time: 00:00:01