scan_led.tan.rpt

Quartus环境下的7段扫描显示电路的源程序

; Slack ; Required tco ; Actual tco ; From    ; To    ; From Clock ;
+-------+--------------+------------+---------+-------+------------+
; N/A   ; None         ; 8.585 ns   ; CNT8[1] ; BT[5] ; CLK        ;
; N/A   ; None         ; 8.573 ns   ; CNT8[1] ; BT[1] ; CLK        ;
; N/A   ; None         ; 8.571 ns   ; CNT8[1] ; BT[0] ; CLK        ;
; N/A   ; None         ; 8.568 ns   ; CNT8[1] ; BT[4] ; CLK        ;
; N/A   ; None         ; 8.558 ns   ; CNT8[1] ; BT[6] ; CLK        ;
; N/A   ; None         ; 8.432 ns   ; CNT8[2] ; BT[5] ; CLK        ;
; N/A   ; None         ; 8.426 ns   ; CNT8[2] ; BT[1] ; CLK        ;
; N/A   ; None         ; 8.411 ns   ; CNT8[2] ; BT[0] ; CLK        ;
; N/A   ; None         ; 8.410 ns   ; CNT8[2] ; BT[4] ; CLK        ;
; N/A   ; None         ; 8.409 ns   ; CNT8[2] ; BT[6] ; CLK        ;
; N/A   ; None         ; 8.283 ns   ; CNT8[1] ; BT[7] ; CLK        ;
; N/A   ; None         ; 8.213 ns   ; CNT8[0] ; BT[5] ; CLK        ;
; N/A   ; None         ; 8.202 ns   ; CNT8[0] ; BT[1] ; CLK        ;
; N/A   ; None         ; 8.201 ns   ; CNT8[0] ; BT[0] ; CLK        ;
; N/A   ; None         ; 8.195 ns   ; CNT8[0] ; BT[4] ; CLK        ;
; N/A   ; None         ; 8.186 ns   ; CNT8[0] ; BT[6] ; CLK        ;
; N/A   ; None         ; 8.125 ns   ; CNT8[0] ; BT[7] ; CLK        ;
; N/A   ; None         ; 8.116 ns   ; CNT8[1] ; BT[2] ; CLK        ;
; N/A   ; None         ; 8.115 ns   ; CNT8[1] ; BT[3] ; CLK        ;
; N/A   ; None         ; 8.019 ns   ; CNT8[2] ; BT[7] ; CLK        ;
; N/A   ; None         ; 7.961 ns   ; CNT8[2] ; BT[3] ; CLK        ;
; N/A   ; None         ; 7.950 ns   ; CNT8[2] ; BT[2] ; CLK        ;
; N/A   ; None         ; 7.780 ns   ; CNT8[1] ; SG[3] ; CLK        ;
; N/A   ; None         ; 7.779 ns   ; CNT8[1] ; SG[4] ; CLK        ;
; N/A   ; None         ; 7.778 ns   ; CNT8[1] ; SG[2] ; CLK        ;
; N/A   ; None         ; 7.777 ns   ; CNT8[1] ; SG[5] ; CLK        ;
; N/A   ; None         ; 7.776 ns   ; CNT8[1] ; SG[1] ; CLK        ;
; N/A   ; None         ; 7.774 ns   ; CNT8[1] ; SG[0] ; CLK        ;
; N/A   ; None         ; 7.745 ns   ; CNT8[0] ; BT[2] ; CLK        ;
; N/A   ; None         ; 7.744 ns   ; CNT8[0] ; BT[3] ; CLK        ;
; N/A   ; None         ; 7.620 ns   ; CNT8[0] ; SG[2] ; CLK        ;
; N/A   ; None         ; 7.613 ns   ; CNT8[0] ; SG[3] ; CLK        ;
; N/A   ; None         ; 7.611 ns   ; CNT8[0] ; SG[4] ; CLK        ;
; N/A   ; None         ; 7.609 ns   ; CNT8[0] ; SG[5] ; CLK        ;
; N/A   ; None         ; 7.609 ns   ; CNT8[0] ; SG[1] ; CLK        ;
; N/A   ; None         ; 7.607 ns   ; CNT8[0] ; SG[0] ; CLK        ;
; N/A   ; None         ; 7.514 ns   ; CNT8[2] ; SG[2] ; CLK        ;
; N/A   ; None         ; 7.496 ns   ; CNT8[2] ; SG[1] ; CLK        ;
; N/A   ; None         ; 7.490 ns   ; CNT8[2] ; SG[3] ; CLK        ;
; N/A   ; None         ; 7.489 ns   ; CNT8[2] ; SG[0] ; CLK        ;
; N/A   ; None         ; 7.483 ns   ; CNT8[2] ; SG[4] ; CLK        ;
; N/A   ; None         ; 7.475 ns   ; CNT8[2] ; SG[5] ; CLK        ;
; N/A   ; None         ; 7.323 ns   ; CNT8[1] ; SG[6] ; CLK        ;
; N/A   ; None         ; 7.159 ns   ; CNT8[0] ; SG[6] ; CLK        ;
; N/A   ; None         ; 7.048 ns   ; CNT8[2] ; SG[6] ; CLK        ;
+-------+--------------+------------+---------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Nov 21 21:21:25 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off scan_led -c scan_led --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "CNT8[1]" and destination register "CNT8[2]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.284 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N5; Fanout = 16; REG Node = 'CNT8[1]'
            Info: 2: + IC(0.677 ns) + CELL(0.607 ns) = 1.284 ns; Loc. = LC_X26_Y9_N0; Fanout = 15; REG Node = 'CNT8[2]'
            Info: Total cell delay = 0.607 ns ( 47.27 % )
            Info: Total interconnect delay = 0.677 ns ( 52.73 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.781 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'CLK'
                Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y9_N0; Fanout = 15; REG Node = 'CNT8[2]'
                Info: Total cell delay = 2.180 ns ( 78.39 % )
                Info: Total interconnect delay = 0.601 ns ( 21.61 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.781 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'CLK'
                Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y9_N5; Fanout = 16; REG Node = 'CNT8[1]'
                Info: Total cell delay = 2.180 ns ( 78.39 % )
                Info: Total interconnect delay = 0.601 ns ( 21.61 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "CLK" to destination pin "BT[5]" through register "CNT8[1]" is 8.585 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'CLK'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y9_N5; Fanout = 16; REG Node = 'CNT8[1]'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.580 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N5; Fanout = 16; REG Node = 'CNT8[1]'
        Info: 2: + IC(1.454 ns) + CELL(0.442 ns) = 1.896 ns; Loc. = LC_X26_Y5_N7; Fanout = 1; COMB Node = 'Mux~392'
        Info: 3: + IC(1.560 ns) + CELL(2.124 ns) = 5.580 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'BT[5]'
        Info: Total cell delay = 2.566 ns ( 45.99 % )
        Info: Total interconnect delay = 3.014 ns ( 54.01 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Nov 21 21:21:26 2006
    Info: Elapsed time: 00:00:01