scan_led.map.qmsg

Quartus环境下的7段扫描显示电路的源程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 21 21:21:10 2006 " "Info: Processing started: Tue Nov 21 21:21:10 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off scan_led -c scan_led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off scan_led -c scan_led" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/04003336 04003338/scan_led.vhd " "Warning: Can't analyze file -- file E:/04003336 04003338/scan_led.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "scan_led.vhd 2 1 " "Warning: Using design file scan_led.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SCAN_LED-one " "Info: Found design unit 1: SCAN_LED-one" {  } { { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SCAN_LED " "Info: Found entity 1: SCAN_LED" {  } { { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "scan_led " "Info: Elaborating entity \"scan_led\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "scan_led.vhd(24) " "Info (10425): VHDL Case Statement information at scan_led.vhd(24): OTHERS choice is never selected" {  } { { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 24 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "scan_led.vhd(43) " "Info (10425): VHDL Case Statement information at scan_led.vhd(43): OTHERS choice is never selected" {  } { { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 43 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "17 " "Info: Implemented 17 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 21 21:21:13 2006 " "Info: Processing ended: Tue Nov 21 21:21:13 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}