scan_led.tan.qmsg

Quartus环境下的7段扫描显示电路的源程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register CNT8\[1\] CNT8\[2\] 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"CNT8\[1\]\" and destination register \"CNT8\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.284 ns + Longest register register " "Info: + Longest register to register delay is 1.284 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT8\[1\] 1 REG LC_X26_Y9_N5 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N5; Fanout = 16; REG Node = 'CNT8\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "" { CNT8[1] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.607 ns) 1.284 ns CNT8\[2\] 2 REG LC_X26_Y9_N0 15 " "Info: 2: + IC(0.677 ns) + CELL(0.607 ns) = 1.284 ns; Loc. = LC_X26_Y9_N0; Fanout = 15; REG Node = 'CNT8\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "1.284 ns" { CNT8[1] CNT8[2] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 47.27 % ) " "Info: Total cell delay = 0.607 ns ( 47.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.677 ns ( 52.73 % ) " "Info: Total interconnect delay = 0.677 ns ( 52.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "1.284 ns" { CNT8[1] CNT8[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.284 ns" { CNT8[1] CNT8[2] } { 0.000ns 0.677ns } { 0.000ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.781 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "" { CLK } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns CNT8\[2\] 2 REG LC_X26_Y9_N0 15 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y9_N0; Fanout = 15; REG Node = 'CNT8\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "1.312 ns" { CLK CNT8[2] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "2.781 ns" { CLK CNT8[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT8[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.781 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "" { CLK } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns CNT8\[1\] 2 REG LC_X26_Y9_N5 16 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y9_N5; Fanout = 16; REG Node = 'CNT8\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "1.312 ns" { CLK CNT8[1] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "2.781 ns" { CLK CNT8[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT8[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "2.781 ns" { CLK CNT8[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT8[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "2.781 ns" { CLK CNT8[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT8[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "1.284 ns" { CNT8[1] CNT8[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.284 ns" { CNT8[1] CNT8[2] } { 0.000ns 0.677ns } { 0.000ns 0.607ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "2.781 ns" { CLK CNT8[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT8[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "2.781 ns" { CLK CNT8[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT8[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "" { CNT8[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { CNT8[2] } {  } {  } } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 29 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK BT\[5\] CNT8\[1\] 8.585 ns register " "Info: tco from clock \"CLK\" to destination pin \"BT\[5\]\" through register \"CNT8\[1\]\" is 8.585 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.781 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "" { CLK } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns CNT8\[1\] 2 REG LC_X26_Y9_N5 16 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y9_N5; Fanout = 16; REG Node = 'CNT8\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "1.312 ns" { CLK CNT8[1] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "2.781 ns" { CLK CNT8[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT8[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.580 ns + Longest register pin " "Info: + Longest register to pin delay is 5.580 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT8\[1\] 1 REG LC_X26_Y9_N5 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N5; Fanout = 16; REG Node = 'CNT8\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "" { CNT8[1] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.454 ns) + CELL(0.442 ns) 1.896 ns Mux~392 2 COMB LC_X26_Y5_N7 1 " "Info: 2: + IC(1.454 ns) + CELL(0.442 ns) = 1.896 ns; Loc. = LC_X26_Y5_N7; Fanout = 1; COMB Node = 'Mux~392'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "1.896 ns" { CNT8[1] Mux~392 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(2.124 ns) 5.580 ns BT\[5\] 3 PIN PIN_77 0 " "Info: 3: + IC(1.560 ns) + CELL(2.124 ns) = 5.580 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'BT\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "3.684 ns" { Mux~392 BT[5] } "NODE_NAME" } "" } } { "scan_led.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.566 ns ( 45.99 % ) " "Info: Total cell delay = 2.566 ns ( 45.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.014 ns ( 54.01 % ) " "Info: Total interconnect delay = 3.014 ns ( 54.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "5.580 ns" { CNT8[1] Mux~392 BT[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.580 ns" { CNT8[1] Mux~392 BT[5] } { 0.000ns 1.454ns 1.560ns } { 0.000ns 0.442ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "2.781 ns" { CLK CNT8[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 CNT8[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/db/scan_led.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led/" "" "5.580 ns" { CNT8[1] Mux~392 BT[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.580 ns" { CNT8[1] Mux~392 BT[5] } { 0.000ns 1.454ns 1.560ns } { 0.000ns 0.442ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 21 21:21:26 2006 " "Info: Processing ended: Tue Nov 21 21:21:26 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}