scan_led.map.rpt

Quartus环境下的7段扫描显示电路的源程序

; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                          ;
+----------------------------------+-----------------+-----------+----------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path                                   ;
+----------------------------------+-----------------+-----------+----------------------------------------------------------------+
; scan_led.vhd                     ; yes             ; Other     ; F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.vhd ;
+----------------------------------+-----------------+-----------+----------------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Total logic elements                        ; 17      ;
;     -- Combinational with no register       ; 14      ;
;     -- Register only                        ; 0       ;
;     -- Combinational with a register        ; 3       ;
;                                             ;         ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 0       ;
;     -- 3 input functions                    ; 15      ;
;     -- 2 input functions                    ; 1       ;
;     -- 1 input functions                    ; 1       ;
;     -- 0 input functions                    ; 0       ;
;         -- Combinational cells for routing  ; 0       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 17      ;
;     -- arithmetic mode                      ; 0       ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 0       ;
;     -- asynchronous clear/load mode         ; 0       ;
;                                             ;         ;
; Total registers                             ; 3       ;
; I/O pins                                    ; 16      ;
; Maximum fan-out node                        ; CNT8[0] ;
; Maximum fan-out                             ; 17      ;
; Total fan-out                               ; 66      ;
; Average fan-out                             ; 2.00    ;
+---------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |SCAN_LED                  ; 17 (17)     ; 3            ; 0           ; 16   ; 0            ; 14 (14)      ; 0 (0)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |SCAN_LED           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/学习课件/大四上/综合课程设计/实验程序/scan_led/scan_led.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Nov 21 21:21:10 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off scan_led -c scan_led
Warning: Can't analyze file -- file E:/04003336 04003338/scan_led.vhd is missing
Warning: Using design file scan_led.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: SCAN_LED-one
    Info: Found entity 1: SCAN_LED
Info: Elaborating entity "scan_led" for the top level hierarchy
Info (10425): VHDL Case Statement information at scan_led.vhd(24): OTHERS choice is never selected
Info (10425): VHDL Case Statement information at scan_led.vhd(43): OTHERS choice is never selected
Info: Implemented 33 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 15 output pins
    Info: Implemented 17 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Nov 21 21:21:13 2006
    Info: Elapsed time: 00:00:03