scan_led1000.fit.qmsg

Quartus环境下的1000进制计数器的扫描显示电路

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 5 17 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 5 total pin(s) used --  17 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 16 10 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 16 total pin(s) used --  10 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.817 ns register register " "Info: Estimated most critical path is register to register delay of 5.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT1000:U1\|C1\[3\] 1 REG LAB_X19_Y7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y7; Fanout = 7; REG Node = 'CNT1000:U1\|C1\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led1000" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/db/scan_led1000.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/" "" "" { CNT1000:U1|C1[3] } "NODE_NAME" } "" } } { "CNT1000.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/CNT1000.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.377 ns) + CELL(0.590 ns) 0.967 ns CNT1000:U1\|process0~361 2 COMB LAB_X18_Y7 3 " "Info: 2: + IC(0.377 ns) + CELL(0.590 ns) = 0.967 ns; Loc. = LAB_X18_Y7; Fanout = 3; COMB Node = 'CNT1000:U1\|process0~361'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led1000" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/db/scan_led1000.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/" "" "0.967 ns" { CNT1000:U1|C1[3] CNT1000:U1|process0~361 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.292 ns) 1.632 ns CNT1000:U1\|add~829 3 COMB LAB_X18_Y7 4 " "Info: 3: + IC(0.373 ns) + CELL(0.292 ns) = 1.632 ns; Loc. = LAB_X18_Y7; Fanout = 4; COMB Node = 'CNT1000:U1\|add~829'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led1000" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/db/scan_led1000.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/" "" "0.665 ns" { CNT1000:U1|process0~361 CNT1000:U1|add~829 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.114 ns) 2.297 ns CNT1000:U1\|add~830 4 COMB LAB_X18_Y7 5 " "Info: 4: + IC(0.551 ns) + CELL(0.114 ns) = 2.297 ns; Loc. = LAB_X18_Y7; Fanout = 5; COMB Node = 'CNT1000:U1\|add~830'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led1000" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/db/scan_led1000.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/" "" "0.665 ns" { CNT1000:U1|add~829 CNT1000:U1|add~830 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 2.962 ns CNT1000:U1\|process0~362 5 COMB LAB_X18_Y7 6 " "Info: 5: + IC(0.223 ns) + CELL(0.442 ns) = 2.962 ns; Loc. = LAB_X18_Y7; Fanout = 6; COMB Node = 'CNT1000:U1\|process0~362'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led1000" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/db/scan_led1000.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/" "" "0.665 ns" { CNT1000:U1|add~830 CNT1000:U1|process0~362 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 3.627 ns CNT1000:U1\|add~833 6 COMB LAB_X18_Y7 2 " "Info: 6: + IC(0.223 ns) + CELL(0.442 ns) = 3.627 ns; Loc. = LAB_X18_Y7; Fanout = 2; COMB Node = 'CNT1000:U1\|add~833'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led1000" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/db/scan_led1000.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/" "" "0.665 ns" { CNT1000:U1|process0~362 CNT1000:U1|add~833 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.114 ns) 4.292 ns CNT1000:U1\|add~834 7 COMB LAB_X18_Y7 4 " "Info: 7: + IC(0.551 ns) + CELL(0.114 ns) = 4.292 ns; Loc. = LAB_X18_Y7; Fanout = 4; COMB Node = 'CNT1000:U1\|add~834'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led1000" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/db/scan_led1000.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/" "" "0.665 ns" { CNT1000:U1|add~833 CNT1000:U1|add~834 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 4.957 ns CNT1000:U1\|process0~364 8 COMB LAB_X18_Y7 2 " "Info: 8: + IC(0.223 ns) + CELL(0.442 ns) = 4.957 ns; Loc. = LAB_X18_Y7; Fanout = 2; COMB Node = 'CNT1000:U1\|process0~364'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led1000" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/db/scan_led1000.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/" "" "0.665 ns" { CNT1000:U1|add~834 CNT1000:U1|process0~364 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.309 ns) 5.817 ns CNT1000:U1\|C2\[0\] 9 REG LAB_X18_Y7 3 " "Info: 9: + IC(0.551 ns) + CELL(0.309 ns) = 5.817 ns; Loc. = LAB_X18_Y7; Fanout = 3; REG Node = 'CNT1000:U1\|C2\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led1000" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/db/scan_led1000.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/" "" "0.860 ns" { CNT1000:U1|process0~364 CNT1000:U1|C2[0] } "NODE_NAME" } "" } } { "CNT1000.vhd" "" { Text "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/CNT1000.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.745 ns ( 47.19 % ) " "Info: Total cell delay = 2.745 ns ( 47.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.072 ns ( 52.81 % ) " "Info: Total interconnect delay = 3.072 ns ( 52.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "scan_led1000" "UNKNOWN" "V1" "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/db/scan_led1000.quartus_db" { Floorplan "F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/" "" "5.817 ns" { CNT1000:U1|C1[3] CNT1000:U1|process0~361 CNT1000:U1|add~829 CNT1000:U1|add~830 CNT1000:U1|process0~362 CNT1000:U1|add~833 CNT1000:U1|add~834 CNT1000:U1|process0~364 CNT1000:U1|C2[0] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 22 10:57:25 2006 " "Info: Processing ended: Wed Nov 22 10:57:25 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}