scan_led.vhd

Quartus环境下的1000进制计数器的扫描显示电路

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SCAN_LED IS
PORT ( CLK : IN STD_LOGIC;
SG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);   --段控制信号输出
BT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; --位控制信号输出
 CP1,CP2,CP3:IN STD_LOGIC_VECTOR(3 DOWNTO 0));           
END;
ARCHITECTURE one OF SCAN_LED IS
SIGNAL CNT8 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
P1: PROCESS( CNT8,CP1,CP2,CP3)
BEGIN
CASE CNT8 IS
WHEN "000" => BT <= "00000001" ; A <="0000";
WHEN "001" => BT <= "00000010" ; A <= "0000" ;
WHEN "010" => BT <= "00000100" ; A <= "0000" ;
WHEN "011" => BT <= "00001000" ; A <= "0000" ;
WHEN "100" => BT <= "00010000" ; A <= "0000" ;
WHEN "101" => BT <= "00100000" ; A <= CP3 ;
WHEN "110" => BT <= "01000000" ; A <= CP2 ;
WHEN "111" => BT <= "10000000" ; A <= CP1 ;
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS P1;
P2: PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK = '1' THEN CNT8 <= CNT8 + 1;
END IF;
END PROCESS P2 ;
P3: PROCESS( A )        --译码电路
BEGIN
CASE A IS
WHEN "0000" => SG<="0111111"; WHEN "0001" => SG<="0000110";
      WHEN "0010" => SG<="1011011"; WHEN "0011" => SG<="1001111";
      WHEN "0100" => SG<="1100110"; WHEN "0101" => SG<="1101101";
      WHEN "0110" => SG<="1111101"; WHEN "0111" => SG<="0000111";
      WHEN "1000" => SG<="1111111"; WHEN "1001" => SG<="1101111";
      WHEN "1010" => SG<="1110111"; WHEN "1011" => SG<="1111100";
      WHEN "1100" => SG<="0111001"; WHEN "1101" => SG<="1011110";
      WHEN "1110" => SG<="1111001"; WHEN "1111" => SG<="1110001";
WHEN OTHERS => NULL ;
END CASE ;
END PROCESS P3;
END;