scan_led1000.tan.rpt

Quartus环境下的1000进制计数器的扫描显示电路

; N/A           ; None        ; -7.514 ns ; EN   ; CNT1000:U1|COUT2 ; CLK0     ;
; N/A           ; None        ; -7.514 ns ; EN   ; CNT1000:U1|COUT1 ; CLK0     ;
; N/A           ; None        ; -7.738 ns ; RST  ; CNT1000:U1|COUT2 ; CLK0     ;
; N/A           ; None        ; -7.738 ns ; RST  ; CNT1000:U1|COUT1 ; CLK0     ;
+---------------+-------------+-----------+------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Nov 22 10:57:29 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off scan_led1000 -c scan_led1000 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK1" is an undefined clock
    Info: Assuming node "CLK0" is an undefined clock
Info: Clock "CLK1" Internal fmax is restricted to 275.03 MHz between source register "SCAN_LED:U2|CNT8[0]" and destination register "SCAN_LED:U2|CNT8[2]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.347 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y6_N9; Fanout = 16; REG Node = 'SCAN_LED:U2|CNT8[0]'
            Info: 2: + IC(0.609 ns) + CELL(0.738 ns) = 1.347 ns; Loc. = LC_X18_Y6_N7; Fanout = 10; REG Node = 'SCAN_LED:U2|CNT8[2]'
            Info: Total cell delay = 0.738 ns ( 54.79 % )
            Info: Total interconnect delay = 0.609 ns ( 45.21 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK1" to destination register is 2.781 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'CLK1'
                Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X18_Y6_N7; Fanout = 10; REG Node = 'SCAN_LED:U2|CNT8[2]'
                Info: Total cell delay = 2.180 ns ( 78.39 % )
                Info: Total interconnect delay = 0.601 ns ( 21.61 % )
            Info: - Longest clock path from clock "CLK1" to source register is 2.781 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 3; CLK Node = 'CLK1'
                Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X18_Y6_N9; Fanout = 16; REG Node = 'SCAN_LED:U2|CNT8[0]'
                Info: Total cell delay = 2.180 ns ( 78.39 % )
                Info: Total interconnect delay = 0.601 ns ( 21.61 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock "CLK0" has Internal fmax of 118.12 MHz between source register "CNT1000:U1|C1[3]" and destination register "CNT1000:U1|C2[3]" (period= 8.466 ns)
    Info: + Longest register to register delay is 8.205 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y7_N8; Fanout = 7; REG Node = 'CNT1000:U1|C1[3]'
        Info: 2: + IC(2.006 ns) + CELL(0.442 ns) = 2.448 ns; Loc. = LC_X18_Y7_N1; Fanout = 3; COMB Node = 'CNT1000:U1|process0~361'
        Info: 3: + IC(0.421 ns) + CELL(0.114 ns) = 2.983 ns; Loc. = LC_X18_Y7_N0; Fanout = 4; COMB Node = 'CNT1000:U1|add~829'
        Info: 4: + IC(0.443 ns) + CELL(0.114 ns) = 3.540 ns; Loc. = LC_X18_Y7_N7; Fanout = 5; COMB Node = 'CNT1000:U1|add~830'
        Info: 5: + IC(0.463 ns) + CELL(0.590 ns) = 4.593 ns; Loc. = LC_X18_Y7_N5; Fanout = 6; COMB Node = 'CNT1000:U1|process0~362'
        Info: 6: + IC(0.832 ns) + CELL(0.292 ns) = 5.717 ns; Loc. = LC_X17_Y7_N1; Fanout = 4; COMB Node = 'rtl~114'
        Info: 7: + IC(0.699 ns) + CELL(0.590 ns) = 7.006 ns; Loc. = LC_X18_Y7_N2; Fanout = 2; COMB Node = 'CNT1000:U1|process0~364'
        Info: 8: + IC(0.461 ns) + CELL(0.738 ns) = 8.205 ns; Loc. = LC_X18_Y7_N6; Fanout = 4; REG Node = 'CNT1000:U1|C2[3]'
        Info: Total cell delay = 2.880 ns ( 35.10 % )
        Info: Total interconnect delay = 5.325 ns ( 64.90 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK0" to destination register is 2.781 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 15; CLK Node = 'CLK0'
            Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X18_Y7_N6; Fanout = 4; REG Node = 'CNT1000:U1|C2[3]'
            Info: Total cell delay = 2.180 ns ( 78.39 % )
            Info: Total interconnect delay = 0.601 ns ( 21.61 % )
        Info: - Longest clock path from clock "CLK0" to source register is 2.781 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 15; CLK Node = 'CLK0'
            Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X19_Y7_N8; Fanout = 7; REG Node = 'CNT1000:U1|C1[3]'
            Info: Total cell delay = 2.180 ns ( 78.39 % )
            Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "CNT1000:U1|COUT2" (data pin = "RST", clock pin = "CLK0") is 7.790 ns
    Info: + Longest pin to register delay is 10.534 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_32; Fanout = 13; PIN Node = 'RST'
        Info: 2: + IC(6.952 ns) + CELL(0.114 ns) = 8.535 ns; Loc. = LC_X17_Y7_N3; Fanout = 3; COMB Node = 'CNT1000:U1|COUT3~1'
        Info: 3: + IC(1.132 ns) + CELL(0.867 ns) = 10.534 ns; Loc. = LC_X19_Y7_N4; Fanout = 1; REG Node = 'CNT1000:U1|COUT2'
        Info: Total cell delay = 2.450 ns ( 23.26 % )
        Info: Total interconnect delay = 8.084 ns ( 76.74 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK0" to destination register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 15; CLK Node = 'CLK0'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X19_Y7_N4; Fanout = 1; REG Node = 'CNT1000:U1|COUT2'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
Info: tco from clock "CLK0" to destination pin "SG[1]" through register "CNT1000:U1|C1[1]" is 12.184 ns
    Info: + Longest clock path from clock "CLK0" to source register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 15; CLK Node = 'CLK0'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X19_Y7_N7; Fanout = 7; REG Node = 'CNT1000:U1|C1[1]'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 9.179 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y7_N7; Fanout = 7; REG Node = 'CNT1000:U1|C1[1]'
        Info: 2: + IC(1.305 ns) + CELL(0.590 ns) = 1.895 ns; Loc. = LC_X18_Y6_N1; Fanout = 1; COMB Node = 'SCAN_LED:U2|A[1]~804'
        Info: 3: + IC(0.440 ns) + CELL(0.590 ns) = 2.925 ns; Loc. = LC_X18_Y6_N4; Fanout = 7; COMB Node = 'SCAN_LED:U2|A[1]~805'
        Info: 4: + IC(1.997 ns) + CELL(0.590 ns) = 5.512 ns; Loc. = LC_X26_Y10_N7; Fanout = 1; COMB Node = 'SCAN_LED:U2|SG[1]~192'
        Info: 5: + IC(1.543 ns) + CELL(2.124 ns) = 9.179 ns; Loc. = PIN_107; Fanout = 0; PIN Node = 'SG[1]'
        Info: Total cell delay = 3.894 ns ( 42.42 % )
        Info: Total interconnect delay = 5.285 ns ( 57.58 % )
Info: th for register "CNT1000:U1|C3[0]" (data pin = "EN", clock pin = "CLK0") is -6.121 ns
    Info: + Longest clock path from clock "CLK0" to destination register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 15; CLK Node = 'CLK0'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X17_Y7_N4; Fanout = 7; REG Node = 'CNT1000:U1|C3[0]'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 8.917 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 13; PIN Node = 'EN'
        Info: 2: + IC(6.581 ns) + CELL(0.867 ns) = 8.917 ns; Loc. = LC_X17_Y7_N4; Fanout = 7; REG Node = 'CNT1000:U1|C3[0]'
        Info: Total cell delay = 2.336 ns ( 26.20 % )
        Info: Total interconnect delay = 6.581 ns ( 73.80 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Nov 22 10:57:29 2006
    Info: Elapsed time: 00:00:01