cnt1000.vhd

Quartus环境下的1000进制计数器的扫描显示电路

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT1000 is 
PORT (CLK,RST,EN: IN STD_LOGIC; 
   CQ1,CQ2,CQ3:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  --个位十位百位输出
   COUT3:OUT STD_LOGIC
); 
END CNT1000; 

ARCHITECTURE behav OF CNT1000 IS
SIGNAL COUT1:STD_LOGIC;
SIGNAL COUT2:STD_LOGIC;
BEGIN
PROCESS(CLK,RST,EN)
VARIABLE C1 ,C2,C3: STD_LOGIC_VECTOR(3 DOWNTO 0);
    
BEGIN
IF RST='1' THEN 
  C1:=(OTHERS=>'0');
  C2:=(OTHERS=>'0');
  C3:=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF EN='1' THEN
         
   IF C1<9 THEN C1:=C1+1;
   ELSE  C1:=(OTHERS=>'0');
   END IF;
   IF C1=9 THEN COUT1<='1';ELSE COUT1<='0';
   END IF;

   IF C1=0 and COUT1='1'
   THEN C2:=C2+1; 
   END IF;
   IF C2=9 THEN COUT2<='1';ELSE COUT2<='0';
   END IF; 
IF C2>9 THEN C2:=(OTHERS=>'0');
   END IF;

   IF C2=0 and COUT2='1'
   THEN C3:=C3+1; 
   END IF;
   IF C3=9 THEN COUT3<='1';ELSE COUT3<='0';
   END IF; 
IF C3>9 THEN C3:=(OTHERS=>'0');
END IF;

   IF C3=0 and C2=0 and C1=0 
   THEN C1:="0000";C2:="0000";C3:="0000";
   END IF;
END IF;
END IF;

CQ1<=C1;
CQ2<=C2;
CQ3<=C3;
END PROCESS;
END behav;