scan_led1000.map.rpt

Quartus环境下的1000进制计数器的扫描显示电路

+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                           ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------+
; scan_led.vhd                     ; yes             ; User VHDL File  ; F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/scan_led.vhd     ;
; scan_led1000.vhd                 ; yes             ; User VHDL File  ; F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/scan_led1000.vhd ;
; CNT1000.vhd                      ; yes             ; Other           ; F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/CNT1000.vhd      ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------+


+-------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                       ;
+---------------------------------------------+---------------------+
; Resource                                    ; Usage               ;
+---------------------------------------------+---------------------+
; Total logic elements                        ; 55                  ;
;     -- Combinational with no register       ; 37                  ;
;     -- Register only                        ; 0                   ;
;     -- Combinational with a register        ; 18                  ;
;                                             ;                     ;
; Logic element usage by number of LUT inputs ;                     ;
;     -- 4 input functions                    ; 28                  ;
;     -- 3 input functions                    ; 21                  ;
;     -- 2 input functions                    ; 5                   ;
;     -- 1 input functions                    ; 1                   ;
;     -- 0 input functions                    ; 0                   ;
;         -- Combinational cells for routing  ; 0                   ;
;                                             ;                     ;
; Logic elements by mode                      ;                     ;
;     -- normal mode                          ; 55                  ;
;     -- arithmetic mode                      ; 0                   ;
;     -- qfbk mode                            ; 0                   ;
;     -- register cascade mode                ; 0                   ;
;     -- synchronous clear/load mode          ; 0                   ;
;     -- asynchronous clear/load mode         ; 12                  ;
;                                             ;                     ;
; Total registers                             ; 18                  ;
; I/O pins                                    ; 20                  ;
; Maximum fan-out node                        ; SCAN_LED:U2|CNT8[0] ;
; Maximum fan-out                             ; 16                  ;
; Total fan-out                               ; 247                 ;
; Average fan-out                             ; 3.29                ;
+---------------------------------------------+---------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                          ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------+
; |SCAN_LED1000              ; 55 (2)      ; 18           ; 0           ; 20   ; 0            ; 37 (2)       ; 0 (0)             ; 18 (0)           ; 0 (0)           ; 0 (0)      ; |SCAN_LED1000             ;
;    |CNT1000:U1|            ; 26 (26)     ; 15           ; 0           ; 0    ; 0            ; 11 (11)      ; 0 (0)             ; 15 (15)          ; 0 (0)           ; 0 (0)      ; |SCAN_LED1000|CNT1000:U1  ;
;    |SCAN_LED:U2|           ; 27 (27)     ; 3            ; 0           ; 0    ; 0            ; 24 (24)      ; 0 (0)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |SCAN_LED1000|SCAN_LED:U2 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 18    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 12    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 15    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; 8:1                ; 4 bits    ; 20 LEs        ; 12 LEs               ; 8 LEs                  ; No         ; |SCAN_LED1000|SCAN_LED:U2|A[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/学习课件/大四上/综合课程设计/实验程序/scan_led1000/scan_led1000.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Nov 22 10:57:18 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off scan_led1000 -c scan_led1000
Warning: Can't analyze file -- file E:/04003336 04003338/scan_led1000/cnt1000.vhd is missing
Info: Found 2 design units, including 1 entities, in source file scan_led.vhd
    Info: Found design unit 1: SCAN_LED-one
    Info: Found entity 1: SCAN_LED
Info: Found 2 design units, including 1 entities, in source file scan_led1000.vhd
    Info: Found design unit 1: SCAN_LED1000-BEHAVE
    Info: Found entity 1: SCAN_LED1000
Info: Elaborating entity "scan_led1000" for the top level hierarchy
Warning: Using design file CNT1000.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: CNT1000-behav
    Info: Found entity 1: CNT1000
Info: Elaborating entity "CNT1000" for hierarchy "CNT1000:U1"
Info: Elaborating entity "SCAN_LED" for hierarchy "SCAN_LED:U2"
Info (10425): VHDL Case Statement information at scan_led.vhd(25): OTHERS choice is never selected
Info (10425): VHDL Case Statement information at scan_led.vhd(44): OTHERS choice is never selected
Info: Implemented 75 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 16 output pins
    Info: Implemented 55 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Nov 22 10:57:22 2006
    Info: Elapsed time: 00:00:04