uart.tcl

一个UART的FPGA core

########## Tcl recorder starts at 01/11/06 17:53:48 ##########

set version "5.1"
set proj_dir "D:/dd"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_fifo.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"baud1.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"decode.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart4_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"data_path.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"dpram16x8.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"inter.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"rcvr.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"txmit.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 01/11/06 17:53:49 ###########


########## Tcl recorder starts at 01/11/06 17:53:55 ##########

# Commands to make the Process: 
# Synplify Synthesize Verilog File
if [catch {open Uart4.cmd w} rspFile] {
	puts stderr "Cannot create response file Uart4.cmd: $rspFile"
} else {
	puts $rspFile "PROJECT: Uart4
working_path: \"$proj_dir\"
module: uart4
verilog_file_list: \"$install_dir/ispcpld/../cae_library/synthesis/verilog/machxo.v\" uart.h data_path.v inter.v dpram16x8.v uart_fifo.v rcvr.v txmit.v baud1.v decode.v uart4_top.v
output_file_name: uart4
suffix_name: edi
write_prf: false
vlog_std_v2001: true
frequency:  400
frequency: 1
fanout_limit:  100
disable_io_insertion: false
force_gsr: auto
package: tqfp144
speed_grade: 3
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/synpwrap\" -rem -e uart4 -target machxo -part lcmxo640c"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete Uart4.cmd

########## Tcl recorder end at 01/11/06 17:53:55 ###########


########## Tcl recorder starts at 01/11/06 17:54:23 ##########

# Commands to make the Process: 
# Map Report
if [runCmd "\"$fpga_bin/edif2ngd\" -l machxo -d lcmxo640c \"uart4.edi\" \"uart4.ngo\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edfupdate\" -t \"uart.tcy\" -w \"uart4.ngo\" -m \"uart4.ngo\" \"uart.ngx\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/ngdbuild\" -a machxo -d lcmxo640c \"uart4.ngo\" \"uart.ngd\" -p \"$install_dir/ispcpld/../ispfpga/machxo/data\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/map\" -a machxo -p lcmxo640c -t tqfp144 -s 3 \"uart.ngd\" -o \"uart_map.ncd\" -mp \"uart.mrp\" \"uart.lpf\" -c 0"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 01/11/06 17:54:23 ###########


########## Tcl recorder starts at 01/11/06 18:01:24 ##########

# Commands to make the Process: 
# Pre-Map Preference Editor
# - none -
# Application to view the Process: 
# Pre-Map Preference Editor
if [runCmd "\"$cpld_bin/prfedit\" -src uart.ngd -premap -a machxo -p lcmxo640c -t tqfp144 -prf uart.lpf -touch uart.ngd"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 01/11/06 18:01:24 ###########


########## Tcl recorder starts at 01/11/06 18:03:51 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart4_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 01/11/06 18:03:51 ###########


########## Tcl recorder starts at 01/11/06 18:07:30 ##########

# Commands to make the Process: 
# Pre-Map Preference Editor
if [catch {open Uart4.cmd w} rspFile] {
	puts stderr "Cannot create response file Uart4.cmd: $rspFile"
} else {
	puts $rspFile "PROJECT: Uart4
working_path: \"$proj_dir\"
module: uart4
verilog_file_list: \"$install_dir/ispcpld/../cae_library/synthesis/verilog/machxo.v\" uart.h data_path.v inter.v dpram16x8.v uart_fifo.v rcvr.v txmit.v baud1.v decode.v uart4_top.v
output_file_name: uart4
suffix_name: edi
write_prf: false
vlog_std_v2001: true
frequency:  400
frequency: 1
fanout_limit:  100
disable_io_insertion: false
force_gsr: auto
package: tqfp144
speed_grade: 3
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/synpwrap\" -rem -e uart4 -target machxo -part lcmxo640c"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete Uart4.cmd
if [runCmd "\"$fpga_bin/edif2ngd\" -l machxo -d lcmxo640c \"uart4.edi\" \"uart4.ngo\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edfupdate\" -t \"uart.tcy\" -w \"uart4.ngo\" -m \"uart4.ngo\" \"uart.ngx\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/ngdbuild\" -a machxo -d lcmxo640c \"uart4.ngo\" \"uart.ngd\" -p \"$install_dir/ispcpld/../ispfpga/machxo/data\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
# Application to view the Process: 
# Pre-Map Preference Editor
if [runCmd "\"$cpld_bin/prfedit\" -src uart.ngd -premap -a machxo -p lcmxo640c -t tqfp144 -prf uart.lpf -touch uart.ngd"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 01/11/06 18:07:30 ###########


########## Tcl recorder starts at 01/11/06 18:09:02 ##########

# Commands to make the Process: 
# Pre-Map Preference Editor
# - none -
# Application to view the Process: 
# Pre-Map Preference Editor
if [runCmd "\"$cpld_bin/prfedit\" -src uart.ngd -premap -a machxo -p lcmxo640c -t tqfp144 -prf uart.lpf -touch uart.ngd"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 01/11/06 18:09:02 ###########


########## Tcl recorder starts at 01/11/06 18:10:41 ##########

# Commands to make the Process: 
# JEDEC File
if [runCmd "\"$fpga_bin/map\" -a machxo -p lcmxo640c -t tqfp144 -s 3 \"uart.ngd\" -o \"uart_map.ncd\" -mp \"uart.mrp\" \"uart.lpf\" -c 0"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open uart.cm2 w} rspFile] {
	puts stderr "Cannot create response file uart.cm2: $rspFile"
} else {
	puts $rspFile "-t uart.mt
-to uart.tw1
-o uart.tcm
-log uart.log
-pr uart.prf
-rpt uart.mrp
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -m -f \"uart.cmm\" -f \"uart.cm2\" -arch machxo \"uart_map.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete uart.cm2
if [catch {open uart.p2t w} rspFile] {
	puts stderr "Cannot create response file uart.p2t: $rspFile"
} else {
	puts $rspFile "-w
-i 6
-l 5
-n 1
-t 1
-s 1
-c 0
-e 0
-exp parplcinlimit=0
-exp parplcinneighborsize=1
-exp parpathbased=off
-exp parhold=on
"
	close $rspFile
}
if [catch {open uart.p3t w} rspFile] {
	puts stderr "Cannot create response file uart.p3t: $rspFile"
} else {
	puts $rspFile "-rem
-log uart.log
-o uart_mp.par
-pr uart.prf
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/multipar\" -p uart.p2t -f \"uart.p3t\" \"uart_map.ncd\" \"uart.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open uart.cm2 w} rspFile] {
	puts stderr "Cannot create response file uart.cm2: $rspFile"
} else {
	puts $rspFile "-t uart.pt
-to uart.twr
-o uart.tcp
-log uart.log
-pr uart.prf
-rpt uart.par
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -p -f \"uart.cmp\" -f \"uart.cm2\" -arch machxo \"uart.ncd\" -l 60"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete uart.cm2
if [catch {open uart.t2b w} rspFile] {
	puts stderr "Cannot create response file uart.t2b: $rspFile"
} else {
	puts $rspFile "-g ES:Yes
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/bitgen\" -f \"uart.t2b\" -w \"uart.ncd\" \"uart.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj uart -if uart.bit -log uart.prm -b2j -oft -jed -of uart.jed -comment uart.alt "] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 01/11/06 18:10:41 ###########


########## Tcl recorder starts at 01/11/06 18:26:01 ##########

# Commands to make the Process: 
# Pre-Map Preference Editor
# - none -
# Application to view the Process: 
# Pre-Map Preference Editor
if [runCmd "\"$cpld_bin/prfedit\" -src uart.ngd -premap -a machxo -p lcmxo640c -t tqfp144 -prf uart.lpf -touch uart.ngd"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 01/11/06 18:26:01 ###########


########## Tcl recorder starts at 01/11/06 18:31:30 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"baud1.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf machxo.v -predefine uart.h"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 01/11/06 18:31:30 ###########


########## Tcl recorder starts at 01/11/06 18:31:39 ##########

# Commands to make the Process: 
# JEDEC File
if [catch {open Uart4.cmd w} rspFile] {
	puts stderr "Cannot create response file Uart4.cmd: $rspFile"
} else {
	puts $rspFile "PROJECT: Uart4
working_path: \"$proj_dir\"
module: uart4
verilog_file_list: \"$install_dir/ispcpld/../cae_library/synthesis/verilog/machxo.v\" uart.h data_path.v inter.v dpram16x8.v uart_fifo.v rcvr.v txmit.v baud1.v decode.v uart4_top.v
output_file_name: uart4
suffix_name: edi
write_prf: false
vlog_std_v2001: true
frequency:  400
frequency: 1
fanout_limit:  100
disable_io_insertion: false
force_gsr: auto
package: tqfp144
speed_grade: 3
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/synpwrap\" -rem -e uart4 -target machxo -part lcmxo640c"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete Uart4.cmd
if [runCmd "\"$fpga_bin/edif2ngd\" -l machxo -d lcmxo640c \"uart4.edi\" \"uart4.ngo\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edfupdate\" -t \"uart.tcy\" -w \"uart4.ngo\" -m \"uart4.ngo\" \"uart.ngx\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/ngdbuild\" -a machxo -d lcmxo640c \"uart4.ngo\" \"uart.ngd\" -p \"$install_dir/ispcpld/../ispfpga/machxo/data\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/map\" -a machxo -p lcmxo640c -t tqfp144 -s 3 \"uart.ngd\" -o \"uart_map.ncd\" -mp \"uart.mrp\" \"uart.lpf\" -c 0"] {
	return
} else {
	vwait done
	if [checkResult $done] {