uart.mrp

一个UART的FPGA core

     u13/un1_AF1_m3_0_1, u13/un1_AF1_m4_0_1
u13/un1_AE1_m5_0_2/SLICE_262 (PFU) covers blocks: u13/un1_AE1_m5_0_2/GATE,
     u13/un1_AE1_m3_0_2, u13/un1_AE1_m4_0_2
u13/un1_FF0_m5_0_4/SLICE_263 (PFU) covers blocks: u13/un1_FF0_m5_0_4/GATE,
     u13/un1_FF0_m3_0_4, u13/un1_FF0_m4_0_4
u13/un1_AF0_m2_0_5/SLICE_264 (PFU) covers blocks: u13/un1_AF0_m2_0_5/GATE,
     u13/un1_AF0_m0_0_5, u13/un1_AF0_m1_0_5
u13/un1_AF0_m5_0_5/SLICE_265 (PFU) covers blocks: u13/un1_AF0_m5_0_5/GATE,
     u13/un1_AF0_m3_0_5, u13/un1_AF0_m4_0_5

                                   Page 12




Design:  Uart4                                         Date:  07/07/06  14:16:57

Symbol Cross Reference (cont)
-----------------------------
u13/un1_AE0_m5_0_6/SLICE_266 (PFU) covers blocks: u13/un1_AE0_m5_0_6/GATE,
     u13/un1_AE0_m3_0_6, u13/un1_AE0_m4_0_6
u13/un1_EF0_m2_0_7/SLICE_267 (PFU) covers blocks: u13/un1_EF0_m2_0_7/GATE,
     u13/un1_EF0_m0_0_7, u13/un1_EF0_m1_0_7
u13/un1_EF0_m5_0_7/SLICE_268 (PFU) covers blocks: u13/un1_EF0_m5_0_7/GATE,
     u13/un1_EF0_m3_0_7, u13/un1_EF0_m4_0_7
u13/un1_EF1_0Z0Z_3/SLICE_269 (PFU) covers blocks: u13/un1_EF1_0Z0Z_3/GATE,
     u13/un1_EF1_0_am_3, u13/un1_EF1_0_bm_3
u13/un1_AE1_m2_0_2/SLICE_270 (PFU) covers blocks: u13/un1_AE1_m2_0_2/GATE,
     u13/un1_AE1_m2_0_am_2, u13/un1_AE1_m2_0_bm_2
u13/un1_AE0_m2_0_6/SLICE_271 (PFU) covers blocks: u13/un1_AE0_m2_0_6/GATE,
     u13/un1_AE0_m2_0_am_6, u13/un1_AE0_m2_0_bm_6
SLICE_272 (PFU) covers blocks: u13/un1_FF0_m1_0_4, u1/inter_pos0_0_a3,
     u1/baud_cs0_0_a2, u8/u1/u0/FF_2, u8/u1/u0/FF_3
SLICE_273 (PFU) covers blocks: u13/un1_FF0_m0_0_4, u1/inter_pos2_0_a3,
     u1/baud_cs0_0_a2, u10/u1/u0/FF_6, u10/u1/u0/FF_7
SLICE_274 (PFU) covers blocks: u13/un1_EF1_m1_0_3, u13/un1_EF1_m1_0_am_3,
     u6/u0/AE, u12/intmask_4__Q, u12/intmask_5__Q
SLICE_275 (PFU) covers blocks: u13/un1_EF1_m0_0_3, u13/un1_EF1_m0_0_am_3,
     u10/u1/AE, u12/intmask_0__Q, u12/intmask_1__Q
SLICE_276 (PFU) covers blocks: u13/un1_FF1_m1_0_0, u13/un1_FF1_m1_0_am_0,
     u6/u0/AF, u9/u1/u0/FF_0, u9/u1/u0/FF_1
SLICE_277 (PFU) covers blocks: u13/un1_FF1_m0_0_0, u13/un1_FF1_m0_0_am_0,
     u10/u1/AF, u8/u1/u0/FF_6, u8/u1/u0/FF_7
SLICE_278 (PFU) covers blocks: u13/un20_data_3, u1/fifor0_cs_0_a2,
     u9/u1/u0/FF_6, u9/u1/u0/FF_7
SLICE_279 (PFU) covers blocks: u13/un20_data_i, u1/fifor3_cs_0_a3
SLICE_280 (PFU) covers blocks: u13/un1_FF1_0Z0Z_0, u13/un1_FF1_m2_0_0,
     u13/un1_FF1_m2s2, u8/u1/u0/FF_4, u8/u1/u0/FF_5
SLICE_281 (PFU) covers blocks: u13/un1_FF0_0Z0Z_4, u13/un1_FF0_m2_0_4,
     u13/un1_FF1_m2s2, u10/u1/u0/FF_4, u10/u1/u0/FF_5
SLICE_282 (PFU) covers blocks: u13/un1_FF1_m2s4, u1/fifor2_cs_0_a2,
     u9/u1/u0/FF_2, u9/u1/u0/FF_3
SLICE_283 (PFU) covers blocks: u13/un1_EF1_m0_0_bm_3, u8/pop, u12/intmask_2__Q,
     u12/intmask_3__Q
SLICE_284 (PFU) covers blocks: u13/un1_EF1_m3_0_3, u1/fifor2_cs_0_a3,
     u12/intmask_6__Q, u12/intmask_7__Q
SLICE_285 (PFU) covers blocks: u13/un1_EF1_m4_0_3, u1/fifor0_cs_0_a3,
     u10/u1/u0/FF_2, u10/u1/u0/FF_3
SLICE_286 (PFU) covers blocks: u12/int_regsr_1, u9/u1/AF, u10/rsr_6__Q,
     u10/rsr_7__Q
SLICE_287 (PFU) covers blocks: u12/int_regsr_2, u12/fifot2_int, u10/u1/u0/FF_0,
     u10/u1/u0/FF_1
SLICE_288 (PFU) covers blocks: u12/int_regsr_0, u12/fifor0_int, u10/rsr_4__Q,
     u10/rsr_5__Q
u10/SLICE_289 (PFU) covers blocks: u10/u1/N_14_i, u10/pop, u10/rsr_2__Q,
     u10/rsr_3__Q
SLICE_290 (PFU) covers blocks: u10/N_12_i, u10/un1_no_bits_rcvd_1,
     u7/u1/u0/FF_4, u7/u1/u0/FF_5
SLICE_291 (PFU) covers blocks: u10/rsr12, u10/state19_p4, u8/u1/u0/FF_0,
     u8/u1/u0/FF_1
SLICE_292 (PFU) covers blocks: u9/u1/N_14_i, u13/un1_FF0_m0_0_am_4, u9/u1/AF,
     u6/u0/u0/FF_6, u6/u0/u0/FF_7
SLICE_293 (PFU) covers blocks: u9/u1/count_0_sqmuxa, u9/pop, u7/u1/u0/FF_0,
     u7/u1/u0/FF_1
SLICE_294 (PFU) covers blocks: u9/N_12_i, u9/un1_no_bits_rcvd_1, u8/rsr_2__Q,

                                   Page 13




Design:  Uart4                                         Date:  07/07/06  14:16:57

Symbol Cross Reference (cont)
-----------------------------
     u8/rsr_3__Q
SLICE_295 (PFU) covers blocks: u9/rsr12, u9/state19_p4, u8/rsr_6__Q, u8/rsr_7__Q
SLICE_296 (PFU) covers blocks: u8/N_12_i, u8/un1_no_bits_rcvd_1, u7/rsr_4__Q,
     u7/rsr_5__Q
SLICE_297 (PFU) covers blocks: u8/rsr12, u8/state19_p4, u7/rsr_6__Q, u7/rsr_7__Q
u7/SLICE_298 (PFU) covers blocks: u7/u1/top13, u7/u1/EF, u7/rsr_2__Q,
     u7/rsr_3__Q
u7/SLICE_299 (PFU) covers blocks: u7/u1/N_14_i, u7/pop, u7/rsr_0__Q, u7/rsr_1__Q
SLICE_300 (PFU) covers blocks: u7/N_12_i, u7/un1_no_bits_rcvd_1, u6/u0/u0/FF_2,
     u6/u0/u0/FF_3
SLICE_301 (PFU) covers blocks: u7/rsr12, u7/state19_p4, u6/u0/u0/FF_4,
     u6/u0/u0/FF_5
u6/SLICE_302 (PFU) covers blocks: u6/u0/N_28_i, u6/un1_EF_1
SLICE_303 (PFU) covers blocks: u6/u0/AE, u6/tsr_0_sqmuxa_i, u5/u0/u0/FF_4,
     u5/u0/u0/FF_5
SLICE_304 (PFU) covers blocks: u6/rd_1_sqmuxa_i, u6/tsr15, u5/u0/u0/FF_2,
     u5/u0/u0/FF_3
u6/SLICE_305 (PFU) covers blocks: u6/un1_EF_2, u6/tsr14, u6/u0/u0/FF_0,
     u6/u0/u0/FF_1
SLICE_306 (PFU) covers blocks: u6/no_bits_sent17, u6/no_bits_sent_c1,
     u5/u0/u0/FF_0, u5/u0/u0/FF_1
SLICE_307 (PFU) covers blocks: u5/u0/count_0_sqmuxa, u13/un1_FF0_m1_0_am_4,
     u5/u0/AF
SLICE_308 (PFU) covers blocks: u5/u0/N_28_i, u5/u0/EF, u4/u0/u0/FF_6,
     u4/u0/u0/FF_7
SLICE_309 (PFU) covers blocks: u5/tsr14, u5/un1_EF_2, u4/u0/u0/FF_2,
     u4/u0/u0/FF_3
SLICE_310 (PFU) covers blocks: u5/tsr_0_sqmuxa_i, u5/tsr14_1, u4/u0/u0/FF_4,
     u4/u0/u0/FF_5
SLICE_311 (PFU) covers blocks: u5/no_bits_sent17, u5/no_bits_sent_c1,
     u4/u0/u0/FF_0, u4/u0/u0/FF_1
SLICE_312 (PFU) covers blocks: u4/tsr14, u4/un1_EF_2, u3/u0/u0/FF_2,
     u3/u0/u0/FF_3
SLICE_313 (PFU) covers blocks: u4/tsr_0_sqmuxa_i, u4/tsr14_1, u3/u0/u0/FF_4,
     u3/u0/u0/FF_5
SLICE_314 (PFU) covers blocks: u4/no_bits_sent17, u4/no_bits_sent_c1,
     u3/u0/u0/FF_0, u3/u0/u0/FF_1
u3/SLICE_315 (PFU) covers blocks: u3/u0/N_28_i, u3/un1_EF_1
u3/SLICE_316 (PFU) covers blocks: u3/u0/AE, u3/tsr_0_sqmuxa_i
u3/SLICE_317 (PFU) covers blocks: u3/rd_1_sqmuxa_i, u3/tsr15
u3/SLICE_318 (PFU) covers blocks: u3/tsr16, u3/un1_EF_2
u3/SLICE_319 (PFU) covers blocks: u3/no_bits_sent17, u3/no_bits_sent_c1
u2/SLICE_320 (PFU) covers blocks: u2/baud_clk1, u2/un4_baud_clk1lto7_0
u2/SLICE_321 (PFU) covers blocks: u2/un2_baud_clk1lto6, u2/un2_baud_clk1lto6_1
u1/SLICE_322 (PFU) covers blocks: u1/baud_cs0_0_a2, u1/inter_mask_0_a3,
     u1/A_2__Q, u1/A_3__Q
u1/SLICE_323 (PFU) covers blocks: u1/baud_cs0_0_a2_0, u1/baud_cs0_0_a2_3,
     u1/A_4__Q
SLICE_324 (PFU) covers blocks: u1/fifor2_cs_0_a2_1, u1/fifot3_cs_0_a3,
     u7/u1/u0/FF_2, u7/u1/u0/FF_3
SLICE_325 (PFU) covers blocks: u4/u0/count_0_sqmuxa, u4/u0/N_28_i,
     u3/u0/u0/FF_6, u3/u0/u0/FF_7
u3/SLICE_326 (PFU) covers blocks: u3/state19, u3/tsr14
u8/SLICE_327 (PFU) covers blocks: u8/u1/N_14_i, u8/u1/count_0_sqmuxa,
     u8/rsr_0__Q, u8/rsr_1__Q
SLICE_328 (PFU) covers blocks: u13/un1_FF1_m5s2, u13/un1_FF1_m2s2,

                                   Page 14




Design:  Uart4                                         Date:  07/07/06  14:16:57

Symbol Cross Reference (cont)
-----------------------------
     u9/u1/u0/FF_4, u9/u1/u0/FF_5
u10/SLICE_329 (PFU) covers blocks: u10/u1/AE, u10/u1/AF, u10/rsr_0__Q,
     u10/rsr_1__Q
u4/SLICE_330 (PFU) covers blocks: u4/u0/top13, u4/un1_EF_1
u2/SLICE_331 (PFU) covers blocks: u2/sys_clk_cnt17_3, u2/un2_baud_clk1lto4_1
u1/SLICE_332 (PFU) covers blocks: u1/N_24_i, u1/inter_mask_0_a3_1, u1/A_0__Q,
     u1/A_1__Q
SLICE_333 (PFU) covers blocks: u10/N_13_i, u7/N_13_i, u7/u1/u0/FF_6,
     u7/u1/u0/FF_7
SLICE_334 (PFU) covers blocks: u9/N_13_i, u8/N_13_i, u8/rsr_4__Q, u8/rsr_5__Q
u3/u0/SLICE_335 (PFU) covers blocks: u3/u0/top13, u3/u0/count_0_sqmuxa
SLICE_336 (PFU) covers blocks: u6/u0/AF, u6/u0/top13, u5/u0/u0/FF_6,
     u5/u0/u0/FF_7
data_0 (PIC/PIO) covers blocks: data_pad_0
inter (PIC/PIO) covers blocks: inter_pad
clk (PIC/PIO) covers blocks: clk_pad
baud_clk1 (PIC/PIO) covers blocks: baud_clk1_pad
we_en1 (PIC/PIO) covers blocks: we_en1_pad
baud_clk (PIC/PIO) covers blocks: baud_clk_pad
txd_3 (PIC/PIO) covers blocks: txd_pad_3
txd_2 (PIC/PIO) covers blocks: txd_pad_2
txd_1 (PIC/PIO) covers blocks: txd_pad_1
txd_0 (PIC/PIO) covers blocks: txd_pad_0
rxd_3 (PIC/PIO) covers blocks: rxd_pad_3
rxd_2 (PIC/PIO) covers blocks: rxd_pad_2
rxd_1 (PIC/PIO) covers blocks: rxd_pad_1
rxd_0 (PIC/PIO) covers blocks: rxd_pad_0
oe_n (PIC/PIO) covers blocks: oe_n_pad
we_n (PIC/PIO) covers blocks: we_n_pad
cs_n (PIC/PIO) covers blocks: cs_n_pad
data_7 (PIC/PIO) covers blocks: data_pad_7
data_6 (PIC/PIO) covers blocks: data_pad_6
data_5 (PIC/PIO) covers blocks: data_pad_5
data_4 (PIC/PIO) covers blocks: data_pad_4
data_3 (PIC/PIO) covers blocks: data_pad_3
data_2 (PIC/PIO) covers blocks: data_pad_2
data_1 (PIC/PIO) covers blocks: data_pad_1
addr_4 (PIC/PIO) covers blocks: addr_pad_4
addr_3 (PIC/PIO) covers blocks: addr_pad_3
addr_2 (PIC/PIO) covers blocks: addr_pad_2
addr_1 (PIC/PIO) covers blocks: addr_pad_1
addr_0 (PIC/PIO) covers blocks: addr_pad_0
rst (PIC/PIO) covers blocks: rst_pad
clk_in (PIC/PIO) covers blocks: clk_in_pad

Signal Cross Reference
----------------------

Signal un1_FF1_0_0 - Driver Comp: SLICE_280:O0
   Load Comps: data_0:I0
Signal u13_un20_data_i_i - Driver Comp: SLICE_279:O0
   Load Comps: data_0:I1, data_7:I1, data_6:I1, data_5:I1, data_4:I1, data_3:I1,
        data_2:I1, data_1:I1
Signal data_in_0 - Driver Comp: data_0:O0
   Load Comps: u6/u0/u0/mem_0_3/SLICE_53:I4, u5/u0/u0/mem_0_3/SLICE_61:I4,
        u4/u0/u0/mem_0_3/SLICE_69:I4, u3/u0/u0/mem_0_3/SLICE_79:I4, SLICE_275:I4

                                   Page 15




Design:  Uart4                                         Date:  07/07/06  14:16:57

Signal Cross Reference (cont)
-----------------------------
Signal u12_int_reg_i - Driver Comp: SLICE_253:O1
   Load Comps: inter:I0
Signal clk_c - Driver Comp: clk:O0
   Load Comps: u10/u1/SLICE_0:I15, u10/u1/SLICE_1:I15, u9/u1/SLICE_2:I15,
        u9/u1/SLICE_3:I15, u8/u1/SLICE_4:I15, u8/u1/SLICE_5:I15,
        u7/u1/SLICE_6:I15, u7/u1/SLICE_7:I15, u6/u0/SLICE_8:I15,
        u6/u0/SLICE_9:I15, u5/u0/SLICE_10:I15, u5/u0/SLICE_11:I15,
        u4/u0/SLICE_12:I15, u4/u0/SLICE_13:I15, u3/u0/SLICE_14:I15,
        u3/u0/SLICE_15:I15, u10/u1/u0/mem_0_3/SLICE_21:I15,
        u10/u1/u0/mem_0_3/SLICE_22:I19, u10/u1/u0/mem_0_2/SLICE_23:I15,
        u10/u1/u0/mem_0_2/SLICE_24:I19, u10/u1/u0/mem_0_1/SLICE_25:I15,
        u10/u1/u0/mem_0_1/SLICE_26:I19, u10/u1/u0/mem_0_0/SLICE_27:I15,
        u10/u1/u0/mem_0_0/SLICE_28:I19, u9/u1/u0/mem_0_3/SLICE_29:I15,
        u9/u1/u0/mem_0_3/SLICE_30:I19, u9/u1/u0/mem_0_2/SLICE_31:I15,
        u9/u1/u0/mem_0_2/SLICE_32:I19, u9/u1/u0/mem_0_1/SLICE_33:I15,
        u9/u1/u0/mem_0_1/SLICE_34:I19, u9/u1/u0/mem_0_0/SLICE_35:I15,
        u9/u1/u0/mem_0_0/SLICE_36:I19, u8/u1/u0/mem_0_3/SLICE_37:I15,
        u8/u1/u0/mem_0_3/SLICE_38:I19, u8/u1/u0/mem_0_2/SLICE_39:I15,
        u8/u1/u0/mem_0_2/SLICE_40:I19, u8/u1/u0/mem_0_1/SLICE_41:I15,
        u8/u1/u0/mem_0_1/SLICE_42:I19, u8/u1/u0/mem_0_0/SLICE_43:I15,
        u8/u1/u0/mem_0_0/SLICE_44:I19, u7/u1/u0/mem_0_3/SLICE_45:I15,
        u7/u1/u0/mem_0_3/SLICE_46:I19, u7/u1/u0/mem_0_2/SLICE_47:I15,
        u7/u1/u0/mem_0_2/SLICE_48:I19, u7/u1/u0/mem_0_1/SLICE_49:I15,
        u7/u1/u0/mem_0_1/SLICE_50:I19, u7/u1/u0/mem_0_0/SLICE_51:I15,
        u7/u1/u0/mem_0_0/SLICE_52:I19, u6/u0/u0/mem_0_3/SLICE_53:I15,
        u6/u0/u0/mem_0_3/SLICE_54:I19, u6/u0/u0/mem_0_2/SLICE_55:I15,
        u6/u0/u0/mem_0_2/SLICE_56:I19, u6/u0/u0/mem_0_1/SLICE_57:I15,
        u6/u0/u0/mem_0_1/SLICE_58:I19, u6/u0/u0/mem_0_0/SLICE_59:I15,
        u6/u0/u0/mem_0_0/SLICE_60:I19, u5/u0/u0/mem_0_3/SLICE_61:I15,
        u5/u0/u0/mem_0_3/SLICE_62:I19, u5/u0/u0/mem_0_2/SLICE_63:I15,
        u5/u0/u0/mem_0_2/SLICE_64:I19, u5/u0/u0/mem_0_1/SLICE_65:I15,
        u5/u0/u0/mem_0_1/SLICE_66:I19, u5/u0/u0/mem_0_0/SLICE_67:I15,
        u5/u0/u0/mem_0_0/SLICE_68:I19, u4/u0/u0/mem_0_3/SLICE_69:I15,
        u4/u0/u0/mem_0_3/SLICE_70:I19, u4/u0/u0/mem_0_2/SLICE_71:I15,
        u4/u0/u0/mem_0_2/SLICE_72:I19, u4/u0/u0/mem_0_1/SLICE_73:I15,
        u4/u0/u0/mem_0_1/SLICE_74:I19, u4/u0/u0/mem_0_0/SLICE_75:I15,
        u4/u0/u0/mem_0_0/SLICE_76:I19, u3/u0/u0/mem_0_0/SLICE_77:I15,
        u3/u0/u0/mem_0_0/SLICE_78:I19, u3/u0/u0/mem_0_3/SLICE_79:I15,
        u3/u0/u0/mem_0_3/SLICE_80:I19, u3/u0/u0/mem_0_2/SLICE_81:I15,
        u3/u0/u0/mem_0_2/SLICE_82:I19, u3/u0/u0/mem_0_1/SLICE_83:I15,
        u3/u0/u0/mem_0_1/SLICE_84:I19, u10/SLICE_106:I15, u10/SLICE_114:I15,
        u10/u1/SLICE_115:I15, u10/u1/SLICE_116:I15, u10/u1/SLICE_117:I15,