uart.mrp

一个UART的FPGA core

u5/u0/u0/mem_0_0/SLICE_68 (PFU) covers blocks: u5/u0/u0/mem_0_0/RAM1
u4/u0/u0/mem_0_3/SLICE_69 (PFU) covers blocks: u4/u0/u0/mem_0_3/RAM0
u4/u0/u0/mem_0_3/SLICE_70 (PFU) covers blocks: u4/u0/u0/mem_0_3/RAM1
u4/u0/u0/mem_0_2/SLICE_71 (PFU) covers blocks: u4/u0/u0/mem_0_2/RAM0

                                    Page 8




Design:  Uart4                                         Date:  07/07/06  14:16:57

Symbol Cross Reference (cont)
-----------------------------
u4/u0/u0/mem_0_2/SLICE_72 (PFU) covers blocks: u4/u0/u0/mem_0_2/RAM1
u4/u0/u0/mem_0_1/SLICE_73 (PFU) covers blocks: u4/u0/u0/mem_0_1/RAM0
u4/u0/u0/mem_0_1/SLICE_74 (PFU) covers blocks: u4/u0/u0/mem_0_1/RAM1
u4/u0/u0/mem_0_0/SLICE_75 (PFU) covers blocks: u4/u0/u0/mem_0_0/RAM0
u4/u0/u0/mem_0_0/SLICE_76 (PFU) covers blocks: u4/u0/u0/mem_0_0/RAM1
u3/u0/u0/mem_0_0/SLICE_77 (PFU) covers blocks: u3/u0/u0/mem_0_0/RAM0
u3/u0/u0/mem_0_0/SLICE_78 (PFU) covers blocks: u3/u0/u0/mem_0_0/RAM1
u3/u0/u0/mem_0_3/SLICE_79 (PFU) covers blocks: u3/u0/u0/mem_0_3/RAM0
u3/u0/u0/mem_0_3/SLICE_80 (PFU) covers blocks: u3/u0/u0/mem_0_3/RAM1
u3/u0/u0/mem_0_2/SLICE_81 (PFU) covers blocks: u3/u0/u0/mem_0_2/RAM0
u3/u0/u0/mem_0_2/SLICE_82 (PFU) covers blocks: u3/u0/u0/mem_0_2/RAM1
u3/u0/u0/mem_0_1/SLICE_83 (PFU) covers blocks: u3/u0/u0/mem_0_1/RAM0
u3/u0/u0/mem_0_1/SLICE_84 (PFU) covers blocks: u3/u0/u0/mem_0_1/RAM1
u3/SLICE_101 (PFU) covers blocks: u3/sdo_8_iv, u3/u0/EF, u3/sdo_Q
u4/SLICE_102 (PFU) covers blocks: u4/sdo_8_iv, u4/tsr16, u4/sdo_Q
u5/SLICE_103 (PFU) covers blocks: u5/sdo_8_iv, u5/tsr16, u5/sdo_Q
u6/SLICE_104 (PFU) covers blocks: u6/sdo_8_iv, u6/tsr16, u6/sdo_Q
u10/SLICE_106 (PFU) covers blocks: u10/baud_clk_enable10, u10/baud_clk_enable_Q
u10/SLICE_107 (PFU) covers blocks: u10/no_bits_rcvd_i_0, u10/no_bits_rcvd_n1,
     u10/no_bits_rcvd_0__Q, u10/no_bits_rcvd_1__Q
u10/SLICE_108 (PFU) covers blocks: u10/no_bits_rcvd_n2, u10/no_bits_rcvd_n3,
     u10/no_bits_rcvd_2__Q, u10/no_bits_rcvd_3__Q
u10/SLICE_114 (PFU) covers blocks: u10/state_7, u10/wr_1_sqmuxa_i, u10/state_Q,
     u10/rxd1_Q
u10/u1/SLICE_115 (PFU) covers blocks: u10/u1/bottom_e0, u10/u1/top13,
     u10/u1/bottom_0__Q
u10/u1/SLICE_116 (PFU) covers blocks: u10/u1/bottom_n1, u10/u1/bottom_n2,
     u10/u1/bottom_1__Q, u10/u1/bottom_2__Q
u10/u1/SLICE_117 (PFU) covers blocks: u10/u1/bottom_n3, u10/u1/bottom_3__Q
u10/u1/SLICE_118 (PFU) covers blocks: u10/u1/top_0__fb, u10/u1/count_0_sqmuxa,
     u10/u1/top_0__Q
u10/u1/SLICE_119 (PFU) covers blocks: u10/u1/un1_top_axbxc1,
     u10/u1/un1_top_axbxc2, u10/u1/top_1__Q, u10/u1/top_2__Q
u10/u1/SLICE_120 (PFU) covers blocks: u10/u1/un1_top_axbxc3,
     u10/u1/top_0__top_i_0, u10/u1/top_3__Q
u10/SLICE_121 (PFU) covers blocks: u10/state_i, u10/wr_Q
u12/SLICE_122 (PFU) covers blocks: u12/int_reg_Q_0, u12/int_regs_i,
     u12/int_reg_Q
u2/SLICE_129 (PFU) covers blocks: u2/sys_clk_cnt_i_0, u2/sys_clk_cnt17_4,
     u2/sys_clk_cnt_0__Q, u2/sys_clk_cnt_6__Q
u2/SLICE_130 (PFU) covers blocks: u2/sys_clk_cnt_5_7, u2/sys_clk_cnt_5_8,
     u2/sys_clk_cnt_7__Q, u2/sys_clk_cnt_8__Q
u3/SLICE_131 (PFU) covers blocks: u3/no_bits_sent_n0, u3/no_bits_sent_n1,
     u3/no_bits_sent_0__Q, u3/no_bits_sent_1__Q
u3/SLICE_132 (PFU) covers blocks: u3/no_bits_sent_n2, u3/no_bits_sent_n3,
     u3/no_bits_sent_2__Q, u3/no_bits_sent_3__Q
u3/SLICE_133 (PFU) covers blocks: u3/state_i, u3/rd_Q
u3/SLICE_134 (PFU) covers blocks: u3/state_7, u3/sdo_1_sqmuxa, u3/state_Q
u3/SLICE_135 (PFU) covers blocks: u3/tmp_Q_0, u3/tmp_Q, u3/tmp1_Q
u3/SLICE_136 (PFU) covers blocks: u3/tsr_7_0, u3/tsr_7_1, u3/tsr_0__Q,
     u3/tsr_1__Q
u3/SLICE_137 (PFU) covers blocks: u3/tsr_7_2, u3/tsr_7_3, u3/tsr_2__Q,
     u3/tsr_3__Q
u3/SLICE_138 (PFU) covers blocks: u3/tsr_7_4, u3/tsr_7_5, u3/tsr_4__Q,
     u3/tsr_5__Q
u3/SLICE_139 (PFU) covers blocks: u3/tsr_7_6, u3/tsr_7_7, u3/tsr_6__Q,

                                    Page 9




Design:  Uart4                                         Date:  07/07/06  14:16:57

Symbol Cross Reference (cont)
-----------------------------
     u3/tsr_7__Q
u3/u0/SLICE_144 (PFU) covers blocks: u3/u0/bottom_e0, u3/u0/bottom_0__Q
u3/u0/SLICE_145 (PFU) covers blocks: u3/u0/bottom_n1, u3/u0/bottom_n2,
     u3/u0/bottom_1__Q, u3/u0/bottom_2__Q
u3/u0/SLICE_146 (PFU) covers blocks: u3/u0/bottom_n3, u3/u0/bottom_3__Q
SLICE_147 (PFU) covers blocks: u3/u0/top_0__fb, u13/un1_FF0_m1_0_bm_4,
     u3/u0/top_0__Q
u3/u0/SLICE_148 (PFU) covers blocks: u3/u0/un1_top_axbxc1, u3/u0/un1_top_axbxc2,
     u3/u0/top_1__Q, u3/u0/top_2__Q
u3/u0/SLICE_149 (PFU) covers blocks: u3/u0/un1_top_axbxc3, u3/u0/top_0__top_i_0,
     u3/u0/top_3__Q
u4/SLICE_150 (PFU) covers blocks: u4/no_bits_sent_n0, u4/no_bits_sent_n1,
     u4/no_bits_sent_0__Q, u4/no_bits_sent_1__Q
u4/SLICE_151 (PFU) covers blocks: u4/no_bits_sent_n2, u4/no_bits_sent_n3,
     u4/no_bits_sent_2__Q, u4/no_bits_sent_3__Q
u4/SLICE_152 (PFU) covers blocks: u4/state_i, u4/rd_1_sqmuxa_i, u4/rd_Q
u4/SLICE_153 (PFU) covers blocks: u4/state_7, u4/tsr15, u4/state_Q
SLICE_154 (PFU) covers blocks: u4/tmp_Q_0, u3/tmpcZ0, u4/tmp_Q, u4/tmp1_Q
u4/SLICE_155 (PFU) covers blocks: u4/tsr_7_0, u4/tsr_7_1, u4/tsr_0__Q,
     u4/tsr_1__Q
u4/SLICE_156 (PFU) covers blocks: u4/tsr_7_2, u4/tsr_7_3, u4/tsr_2__Q,
     u4/tsr_3__Q
u4/SLICE_157 (PFU) covers blocks: u4/tsr_7_4, u4/tsr_7_5, u4/tsr_4__Q,
     u4/tsr_5__Q
u4/SLICE_158 (PFU) covers blocks: u4/tsr_7_6, u4/tsr_7_7, u4/tsr_6__Q,
     u4/tsr_7__Q
SLICE_163 (PFU) covers blocks: u4/u0/bottom_e0, u13/un1_EF1_m1_0_bm_3,
     u4/u0/bottom_0__Q
u4/u0/SLICE_164 (PFU) covers blocks: u4/u0/bottom_n1, u4/u0/bottom_n2,
     u4/u0/bottom_1__Q, u4/u0/bottom_2__Q
u4/u0/SLICE_165 (PFU) covers blocks: u4/u0/bottom_n3, u4/u0/bottom_3__Q
SLICE_166 (PFU) covers blocks: u4/u0/top_0__fb, u13/un1_FF1_m1_0_bm_0,
     u4/u0/top_0__Q
u4/u0/SLICE_167 (PFU) covers blocks: u4/u0/un1_top_axbxc1, u4/u0/un1_top_axbxc2,
     u4/u0/top_1__Q, u4/u0/top_2__Q
u4/u0/SLICE_168 (PFU) covers blocks: u4/u0/un1_top_axbxc3, u4/u0/top_0__top_i_0,
     u4/u0/top_3__Q
u4/SLICE_169 (PFU) covers blocks: u4/we_en_Q_0/GATE, u4/we_en_Q_0_bm, u4/we_en_Q
u5/SLICE_170 (PFU) covers blocks: u5/no_bits_sent_n0, u5/no_bits_sent_n1,
     u5/no_bits_sent_0__Q, u5/no_bits_sent_1__Q
u5/SLICE_171 (PFU) covers blocks: u5/no_bits_sent_n2, u5/no_bits_sent_n3,
     u5/no_bits_sent_2__Q, u5/no_bits_sent_3__Q
u5/SLICE_172 (PFU) covers blocks: u5/state_i, u5/rd_1_sqmuxa_i, u5/rd_Q
u5/SLICE_173 (PFU) covers blocks: u5/state_7, u5/tsr15, u5/state_Q
u5/SLICE_174 (PFU) covers blocks: u5/tmp_Q_0, u5/tmp_Q, u5/tmp1_Q
u5/SLICE_175 (PFU) covers blocks: u5/tsr_7_0, u5/tsr_7_1, u5/tsr_0__Q,
     u5/tsr_1__Q
u5/SLICE_176 (PFU) covers blocks: u5/tsr_7_2, u5/tsr_7_3, u5/tsr_2__Q,
     u5/tsr_3__Q
u5/SLICE_177 (PFU) covers blocks: u5/tsr_7_4, u5/tsr_7_5, u5/tsr_4__Q,
     u5/tsr_5__Q
u5/SLICE_178 (PFU) covers blocks: u5/tsr_7_6, u5/tsr_7_7, u5/tsr_6__Q,
     u5/tsr_7__Q
u5/u0/SLICE_183 (PFU) covers blocks: u5/u0/bottom_e0, u5/u0/top13,
     u5/u0/bottom_0__Q
u5/u0/SLICE_184 (PFU) covers blocks: u5/u0/bottom_n1, u5/u0/bottom_n2,

                                   Page 10




Design:  Uart4                                         Date:  07/07/06  14:16:57

Symbol Cross Reference (cont)
-----------------------------
     u5/u0/bottom_1__Q, u5/u0/bottom_2__Q
u5/u0/SLICE_185 (PFU) covers blocks: u5/u0/bottom_n3, u5/u0/bottom_3__Q
u5/SLICE_186 (PFU) covers blocks: u5/u0/top_0__fb, u5/un1_EF_1, u5/u0/top_0__Q
u5/u0/SLICE_187 (PFU) covers blocks: u5/u0/un1_top_axbxc1, u5/u0/un1_top_axbxc2,
     u5/u0/top_1__Q, u5/u0/top_2__Q
u5/u0/SLICE_188 (PFU) covers blocks: u5/u0/un1_top_axbxc3, u5/u0/top_0__top_i_0,
     u5/u0/top_3__Q
SLICE_189 (PFU) covers blocks: u5/we_en_Q_0, u1/fifot2_cs_0_a3, u5/we_en_Q
u6/SLICE_190 (PFU) covers blocks: u6/no_bits_sent_n0, u6/no_bits_sent_n1,
     u6/no_bits_sent_0__Q, u6/no_bits_sent_1__Q
u6/SLICE_191 (PFU) covers blocks: u6/no_bits_sent_n2, u6/no_bits_sent_n3,
     u6/no_bits_sent_2__Q, u6/no_bits_sent_3__Q
u6/SLICE_192 (PFU) covers blocks: u6/state_i, u6/rd_Q
u6/SLICE_193 (PFU) covers blocks: u6/state_7/GATE, u6/state_7_am, u6/state_7_bm,
     u6/state_Q
u6/SLICE_194 (PFU) covers blocks: u6/tmp_Q_0, u6/tmpcZ0, u6/tmp_Q, u6/tmp1_Q
u6/SLICE_195 (PFU) covers blocks: u6/tsr_7_0, u6/tsr_7_1, u6/tsr_0__Q,
     u6/tsr_1__Q
u6/SLICE_196 (PFU) covers blocks: u6/tsr_7_2, u6/tsr_7_3, u6/tsr_2__Q,
     u6/tsr_3__Q
u6/SLICE_197 (PFU) covers blocks: u6/tsr_7_4, u6/tsr_7_5, u6/tsr_4__Q,
     u6/tsr_5__Q
u6/SLICE_198 (PFU) covers blocks: u6/tsr_7_6, u6/tsr_7_7, u6/tsr_6__Q,
     u6/tsr_7__Q
u6/u0/SLICE_203 (PFU) covers blocks: u6/u0/bottom_e0, u6/u0/bottom_0__Q
u6/u0/SLICE_204 (PFU) covers blocks: u6/u0/bottom_n1, u6/u0/bottom_n2,
     u6/u0/bottom_1__Q, u6/u0/bottom_2__Q
u6/u0/SLICE_205 (PFU) covers blocks: u6/u0/bottom_n3, u6/u0/bottom_3__Q
u6/u0/SLICE_206 (PFU) covers blocks: u6/u0/top_0__fb, u6/u0/count_0_sqmuxa,
     u6/u0/top_0__Q
u6/u0/SLICE_207 (PFU) covers blocks: u6/u0/un1_top_axbxc1, u6/u0/un1_top_axbxc2,
     u6/u0/top_1__Q, u6/u0/top_2__Q
u6/u0/SLICE_208 (PFU) covers blocks: u6/u0/un1_top_axbxc3, u6/u0/top_0__top_i_0,
     u6/u0/top_3__Q
SLICE_209 (PFU) covers blocks: u6/we_en_Q_0, u1/baud_cs0_0_a2_2, u6/we_en_Q
u7/SLICE_210 (PFU) covers blocks: u7/baud_clk_enable10, u7/baud_clk_enable_Q
u7/SLICE_211 (PFU) covers blocks: u7/no_bits_rcvd_i_0, u7/no_bits_rcvd_n1,
     u7/no_bits_rcvd_0__Q, u7/no_bits_rcvd_1__Q
u7/SLICE_212 (PFU) covers blocks: u7/no_bits_rcvd_n2, u7/no_bits_rcvd_n3,
     u7/no_bits_rcvd_2__Q, u7/no_bits_rcvd_3__Q
u7/SLICE_218 (PFU) covers blocks: u7/state_7, u7/wr_1_sqmuxa_i, u7/state_Q,
     u7/rxd1_Q
u7/u1/SLICE_219 (PFU) covers blocks: u7/u1/bottom_e0, u7/u1/count_0_sqmuxa,
     u7/u1/bottom_0__Q
u7/u1/SLICE_220 (PFU) covers blocks: u7/u1/bottom_n1, u7/u1/bottom_n2,
     u7/u1/bottom_1__Q, u7/u1/bottom_2__Q
u7/u1/SLICE_221 (PFU) covers blocks: u7/u1/bottom_n3, u7/u1/bottom_3__Q
SLICE_222 (PFU) covers blocks: u7/u1/top_0__fb, u13/un1_FF0_m0_0_bm_4,
     u7/u1/top_0__Q
u7/u1/SLICE_223 (PFU) covers blocks: u7/u1/un1_top_axbxc1, u7/u1/un1_top_axbxc2,
     u7/u1/top_1__Q, u7/u1/top_2__Q
u7/u1/SLICE_224 (PFU) covers blocks: u7/u1/un1_top_axbxc3, u7/u1/top_0__top_i_0,
     u7/u1/top_3__Q
u7/SLICE_225 (PFU) covers blocks: u7/state_i, u7/wr_Q
u8/SLICE_226 (PFU) covers blocks: u8/baud_clk_enable10, u8/baud_clk_enable_Q
u8/SLICE_227 (PFU) covers blocks: u8/no_bits_rcvd_i_0, u8/no_bits_rcvd_n1,

                                   Page 11




Design:  Uart4                                         Date:  07/07/06  14:16:57

Symbol Cross Reference (cont)
-----------------------------
     u8/no_bits_rcvd_0__Q, u8/no_bits_rcvd_1__Q
u8/SLICE_228 (PFU) covers blocks: u8/no_bits_rcvd_n2, u8/no_bits_rcvd_n3,
     u8/no_bits_rcvd_2__Q, u8/no_bits_rcvd_3__Q
u8/SLICE_234 (PFU) covers blocks: u8/state_7, u8/wr_1_sqmuxa_i, u8/state_Q,
     u8/rxd1_Q
u8/u1/SLICE_235 (PFU) covers blocks: u8/u1/bottom_e0, u8/u1/top13,
     u8/u1/bottom_0__Q
u8/u1/SLICE_236 (PFU) covers blocks: u8/u1/bottom_n1, u8/u1/bottom_n2,
     u8/u1/bottom_1__Q, u8/u1/bottom_2__Q
u8/u1/SLICE_237 (PFU) covers blocks: u8/u1/bottom_n3, u8/u1/bottom_3__Q
SLICE_238 (PFU) covers blocks: u8/u1/top_0__fb, u13/un1_FF1_m0_0_bm_0,
     u8/u1/top_0__Q
u8/u1/SLICE_239 (PFU) covers blocks: u8/u1/un1_top_axbxc1, u8/u1/un1_top_axbxc2,
     u8/u1/top_1__Q, u8/u1/top_2__Q
u8/u1/SLICE_240 (PFU) covers blocks: u8/u1/un1_top_axbxc3, u8/u1/top_0__top_i_0,
     u8/u1/top_3__Q
u8/SLICE_241 (PFU) covers blocks: u8/state_i, u8/wr_Q
u9/SLICE_242 (PFU) covers blocks: u9/baud_clk_enable10, u9/baud_clk_enable_Q
u9/SLICE_243 (PFU) covers blocks: u9/no_bits_rcvd_i_0, u9/no_bits_rcvd_n1,
     u9/no_bits_rcvd_0__Q, u9/no_bits_rcvd_1__Q
u9/SLICE_244 (PFU) covers blocks: u9/no_bits_rcvd_n2, u9/no_bits_rcvd_n3,
     u9/no_bits_rcvd_2__Q, u9/no_bits_rcvd_3__Q
SLICE_245 (PFU) covers blocks: u2/baud_clklto8, u9/rsr_0__Q, u9/rsr_1__Q
SLICE_246 (PFU) covers blocks: u5/state19, u4/state19, u9/rsr_2__Q, u9/rsr_3__Q
SLICE_247 (PFU) covers blocks: u7/un3_p4, u5/u0/AF, u9/rsr_4__Q, u9/rsr_5__Q
SLICE_248 (PFU) covers blocks: u9/un3_p4, u8/un3_p4, u9/rsr_6__Q, u9/rsr_7__Q
SLICE_249 (PFU) covers blocks: u10/un3_p4, u9/u1/AE, u9/rxd1_Q
u9/SLICE_250 (PFU) covers blocks: u9/state_7, u9/wr_1_sqmuxa_i, u9/state_Q
u9/u1/SLICE_251 (PFU) covers blocks: u9/u1/bottom_e0, u9/u1/EF,
     u9/u1/bottom_0__Q
u9/u1/SLICE_252 (PFU) covers blocks: u9/u1/bottom_n1, u9/u1/bottom_n2,
     u9/u1/bottom_1__Q, u9/u1/bottom_2__Q
SLICE_253 (PFU) covers blocks: u9/u1/bottom_n3, u12/int_reg_int_reg_i,
     u9/u1/bottom_3__Q
u9/u1/SLICE_254 (PFU) covers blocks: u9/u1/top_0__fb, u9/u1/top13,
     u9/u1/top_0__Q
u9/u1/SLICE_255 (PFU) covers blocks: u9/u1/un1_top_axbxc1, u9/u1/un1_top_axbxc2,
     u9/u1/top_1__Q, u9/u1/top_2__Q
u9/u1/SLICE_256 (PFU) covers blocks: u9/u1/un1_top_axbxc3, u9/u1/top_0__top_i_0,
     u9/u1/top_3__Q
SLICE_257 (PFU) covers blocks: u9/state_i, u12/fifot1_int, u9/wr_Q
u3/SLICE_258 (PFU) covers blocks: u3/we_en_Q_0/GATE, u3/we_en_Q_0_bm, u3/we_en_Q
u13/un1_FF1_m5_0_0/SLICE_259 (PFU) covers blocks: u13/un1_FF1_m5_0_0/GATE,
     u13/un1_FF1_m3_0_0, u13/un1_FF1_m4_0_0
u13/un1_AF1_m2_0_1/SLICE_260 (PFU) covers blocks: u13/un1_AF1_m2_0_1/GATE,
     u13/un1_AF1_m0_0_1, u13/un1_AF1_m1_0_1
u13/un1_AF1_m5_0_1/SLICE_261 (PFU) covers blocks: u13/un1_AF1_m5_0_1/GATE,