uart.mrp

一个UART的FPGA core

                Lattice Mapping Report File for Design 'Uart4'

Design Information
------------------

Command line:   d:\ispTOOLS5_1\ispfpga\bin\nt\map.exe -a MachXO -p LCMXO640C -t
     TQFP144 -s 3 uart.ngd -o uart_map.ncd -mp uart.mrp uart.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO640CTQFP144
Target Speed:   3
Mapper:  mj5g00,  version:  ispLever_v51_SP2_Build (10)
Mapped on:  07/07/06  14:16:57

Design Summary
--------------

   Number of PFU registers:    319
   Number of SLICEs:           283 out of   320 (88%)
      SLICEs(logic/ROM):       128 out of   128 (100%)
      SLICEs(logic/ROM/RAM):   155 out of   192 (81%)
          As RAM:           64
          As Logic/ROM:     91
   Number of logic LUT4s:     375
   Number of distributed RAM:  64 (128 LUT4s)
   Number of ripple logic:     21 (42 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:     545
   Number of external PIOs: 31 out of 113 (27%)
   Number of 3-state buffers:   0
   Number of GSRs:  0 out of 1 (0%)
   JTAG used :      Yes
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   Number of TSALL: 0 out of 1 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  4
     Net clk_c: 165 loads, 161 rising, 4 falling (Driver: PIO clk )
     Net baud_clk1_c: 16 loads, 16 rising, 0 falling (Driver: u2/baud_clk1 )
     Net baud_clk_c: 36 loads, 36 rising, 0 falling (Driver: u2/baud_clklto8 )
     Net clk_in_c: 5 loads, 5 rising, 0 falling (Driver: PIO clk_in )
   Number of Clock Enables:  42
     Net inter_mask: 4 loads, 4 LSLICEs
     Net u10/popZ0: 6 loads, 6 LSLICEs
     Net u10/u1/N_14_iZ0: 2 loads, 2 LSLICEs
     Net u10/wr_1_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u10/rsrZ0Z12: 4 loads, 4 LSLICEs
     Net u10/N_12_iZ0: 1 loads, 1 LSLICEs
     Net u9/popZ0: 6 loads, 6 LSLICEs
     Net u9/u1/N_14_iZ0: 2 loads, 2 LSLICEs
     Net u9/wr_1_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u9/rsrZ0Z12: 4 loads, 4 LSLICEs
     Net u9/N_12_iZ0: 1 loads, 1 LSLICEs
     Net u8/popZ0: 6 loads, 6 LSLICEs
     Net u8/u1/N_14_iZ0: 2 loads, 2 LSLICEs
     Net u8/wr_1_sqmuxa_iZ0: 1 loads, 1 LSLICEs

                                    Page 1




Design:  Uart4                                         Date:  07/07/06  14:16:57

Design Summary (cont)
---------------------
     Net u8/rsrZ0Z12: 4 loads, 4 LSLICEs
     Net u8/N_12_iZ0: 1 loads, 1 LSLICEs
     Net u7/popZ0: 6 loads, 6 LSLICEs
     Net u7/u1/N_14_iZ0: 2 loads, 2 LSLICEs
     Net u7/wr_1_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u7/rsrZ0Z12: 4 loads, 4 LSLICEs
     Net u7/N_12_iZ0: 1 loads, 1 LSLICEs
     Net u6/un1_EF_1_2: 6 loads, 6 LSLICEs
     Net u6/u0/N_28_iZ0: 2 loads, 2 LSLICEs
     Net u6/tsr_0_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u6/un1_EF_2_2: 4 loads, 4 LSLICEs
     Net u6/rd_1_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u5/un1_EF_1_1: 6 loads, 6 LSLICEs
     Net u5/u0/N_28_iZ0: 2 loads, 2 LSLICEs
     Net u5/tsr_0_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u5/un1_EF_2_1: 4 loads, 4 LSLICEs
     Net u5/rd_1_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u4/un1_EF_1_0: 6 loads, 6 LSLICEs
     Net u4/u0/N_28_iZ0: 2 loads, 2 LSLICEs
     Net u4/tsr_0_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u4/un1_EF_2_0: 4 loads, 4 LSLICEs
     Net u4/rd_1_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u3/rd_1_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u3/tsr_0_sqmuxa_iZ0: 1 loads, 1 LSLICEs
     Net u3/un1_EFZ0Z_1: 6 loads, 6 LSLICEs
     Net u3/u0/N_28_iZ0: 2 loads, 2 LSLICEs
     Net u3/un1_EFZ0Z_2: 4 loads, 4 LSLICEs
     Net u1/N_24_iZ0: 3 loads, 3 LSLICEs
   Number of LSRs:  13
     Net rst_c: 166 loads, 166 LSLICEs
     Net u10/wr: 8 loads, 8 LSLICEs
     Net u10/N_13_iZ0: 2 loads, 2 LSLICEs
     Net u9/wr: 8 loads, 8 LSLICEs
     Net u9/N_13_iZ0: 2 loads, 2 LSLICEs
     Net u8/wr: 8 loads, 8 LSLICEs
     Net u8/N_13_iZ0: 2 loads, 2 LSLICEs
     Net u7/wr: 8 loads, 8 LSLICEs
     Net u7/N_13_iZ0: 2 loads, 2 LSLICEs
     Net u6/we_en4: 8 loads, 8 LSLICEs
     Net u5/we_en3: 8 loads, 8 LSLICEs
     Net u4/we_en2: 8 loads, 8 LSLICEs
     Net we_en1_c: 8 loads, 8 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net rst_c: 170 loads
     Net u1_A_4: 21 loads
     Net u1_A_0: 18 loads
     Net we_en1_c: 16 loads
     Net u10/wr: 15 loads
     Net u4/we_en2: 15 loads
     Net u5/we_en3: 15 loads
     Net u6/we_en4: 15 loads
     Net u7/wr: 15 loads
     Net u8/wr: 15 loads



                                    Page 2




Design:  Uart4                                         Date:  07/07/06  14:16:57

IO (PIO) Attributes
-------------------

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| data_0              | BIDIR     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| inter               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| clk                 | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| baud_clk1           | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| we_en1              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| baud_clk            | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| txd_3               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| txd_2               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| txd_1               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| txd_0               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| rxd_3               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| rxd_2               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| rxd_1               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| rxd_0               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| oe_n                | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| we_n                | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| cs_n                | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| data_7              | BIDIR     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| data_6              | BIDIR     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| data_5              | BIDIR     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| data_4              | BIDIR     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| data_3              | BIDIR     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| data_2              | BIDIR     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| data_1              | BIDIR     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| addr_4              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| addr_3              | INPUT     | LVCMOS33  |            |

                                    Page 3




Design:  Uart4                                         Date:  07/07/06  14:16:57

IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+
| addr_2              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| addr_1              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| addr_0              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| rst                 | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| clk_in              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+

Removed logic
-------------

Block GSR_INST undriven or does not drive anything - clipped.
Signal clk_c_iZ0 was merged into signal clk_c
Signal u2/un6_sys_clk_cnt_axbZ0Z_0 was merged into signal u2/sys_clk_cnt_0
Signal u2/un6_sys_clk_cnt_axbZ0Z_1 was merged into signal u2/sys_clk_cnt_1
Signal u2/un6_sys_clk_cnt_axbZ0Z_2 was merged into signal u2/sys_clk_cnt_2
Signal u2/un6_sys_clk_cnt_axbZ0Z_3 was merged into signal u2/sys_clk_cnt_3
Signal u2/un6_sys_clk_cnt_axbZ0Z_4 was merged into signal u2/sys_clk_cnt_4
Signal u2/un6_sys_clk_cnt_axbZ0Z_5 was merged into signal u2/sys_clk_cnt_5
Signal u2/un6_sys_clk_cnt_axbZ0Z_6 was merged into signal u2/sys_clk_cnt_6
Signal u2/un6_sys_clk_cnt_axbZ0Z_7 was merged into signal u2/sys_clk_cnt_7
Signal u2/un6_sys_clk_cnt_axbZ0Z_8 was merged into signal u2/sys_clk_cnt_8
Signal u3/u0/u0/dec_wre3 was merged into signal we_en1_c
Signal u4/u0/u0/dec_wre3 was merged into signal u4/we_en2
Signal u5/u0/u0/dec_wre3 was merged into signal u5/we_en3
Signal u6/u0/u0/dec_wre3 was merged into signal u6/we_en4
Signal u7/u1/u0/dec_wre3 was merged into signal u7/wr
Signal u8/u1/u0/dec_wre3 was merged into signal u8/wr
Signal u9/u1/u0/dec_wre3 was merged into signal u9/wr
Signal u10/u1/u0/dec_wre3 was merged into signal u10/wr
Signal u3/Q_0_am_0 undriven or does not drive anything - clipped.
Signal u4/Q_0_am undriven or does not drive anything - clipped.
Signal GNDZ0 undriven or does not drive anything - clipped.
Signal VCCZ0 undriven or does not drive anything - clipped.
Signal u2/un6_sys_clk_cnt_cry_2_0_COUT0 undriven or does not drive anything -
     clipped.
Signal u2/un6_sys_clk_cnt_cry_4_0_COUT0 undriven or does not drive anything -
     clipped.
Signal u2/un6_sys_clk_cnt_cry_6_0_COUT0 undriven or does not drive anything -
     clipped.
Signal u2/NC1 undriven or does not drive anything - clipped.
Signal u2/NC0 undriven or does not drive anything - clipped.
Signal u2/un6_sys_clk_cnt_s_8_0_COUT0 undriven or does not drive anything -
     clipped.
Signal u2/un6_sys_clk_cnt_cry_0_0_S0 undriven or does not drive anything -
     clipped.
Signal u2/un6_sys_clk_cnt_cry_0_0_COUT0 undriven or does not drive anything -
     clipped.
Signal u3/u0/un1_count_1_cry_0_0_COUT0 undriven or does not drive anything -
     clipped.
Signal u3/u0/un1_count_1_cry_2_0_COUT1 undriven or does not drive anything -
     clipped.