turbopack.vhd

turbo码的verilog程序

                res2    : out std_logic;        -- partial code of the minimum value
                res3    : out std_logic         -- partial code of the minimum value
                );
    end component;
    
    component accDistSel
        port    (
                accDist     : in  ARRAY32c; -- array of 32 accumulated distances
                accDistCod  : out ARRAY8b;  -- array of 8 2-bit selection signals
                accDistOut  : out ARRAY8a   -- array of 8 selected accumulated distances
                );
    end component;
    
    component cod2
        port    (
                in1     : in  std_logic;                    -- 1-bit first input signal
                in2     : in  std_logic;                    -- 1-bit second input signal
                in3     : in  std_logic;                    -- 1-bit third input signal
                outCod  : out std_logic_vector(1 downto 0)  -- 2-bit coded value
                );
    end component;
    
    component min8
        port    (
                op  : in  ARRAY8a;                      -- input signals
                res : out std_logic_vector(6 downto 0)  -- code of the minimum value
                );
    end component;
    
    component cod3
        port    (
                inSig   : in  std_logic_vector(6 downto 0); -- 7 1-bit input signals
                outCod  : out std_logic_vector(2 downto 0)  -- 3-bit coded value
                );
    end component;
    
    component stateSel
        port    (
                stateDist   : in ARRAY8a;                       -- state accumulated distance
                selState    : out std_logic_vector(2 downto 0)  -- selected state code
                );
    end component;
    
    component acs
        port    (
                clk         : in  std_logic;                            -- clock
                rst         : in  std_logic;                            -- negative reset
                a           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                b           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                y           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                w           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                z           : in  ARRAY4c;                              -- extrinsic information array
                selStateL   : in  std_logic_vector(2 downto 0);         -- selected state at t = L
                selTransL   : in  std_logic_vector(1 downto 0);         -- selected transition at selStateL
                selState    : out std_logic_vector(2 downto 0);         -- selected state
                stateDist   : out ARRAY8b;                              -- selected accumulated distances (per state)
                weight      : out ARRAY4a                               -- four weights sorted by transition code
                );
    end component;
    
    component trellis1
        port    (
                clk         : in  std_logic;                    -- clock
                rst         : in  std_logic;                    -- negative reset
                selState    : in  std_logic_vector(2 downto 0); -- selected state at time 0
                selTrans    : in  ARRAY8b;                      -- 8 selected transitions (1 per state) at time 0
                selStateL2  : out std_logic_vector(2 downto 0); -- selected state at time (l - 2)
                selStateL1  : out std_logic_vector(2 downto 0); -- selected state at time (l - 1)
                stateL1     : out ARRAY4d;                      -- 4 possible states at time (l - 1)
                selTransL2  : out std_logic_vector(1 downto 0)  -- selected transition at time (l - 2)
                );
    end component;
    
    component trellis2
        port    (
                clk         : in  std_logic;                    -- clock
                rst         : in  std_logic;                    -- negative reset
                selState    : in  std_logic_vector(2 downto 0); -- selected state at time (l - 1)
                state       : in  ARRAY4d;                      -- 4 possible states at time (l - 1)
                selTrans    : in  ARRAY8b;                      -- 8 selected transitions (1 per state) at time (l - 1)
                weight      : in  ARRAY4a;                      -- four weights sorted by transition code at time (l - 1)
                llr0        : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (0, 0) at time (l + m - 1)
                llr1        : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (0, 1) at time (l + m - 1)
                llr2        : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (1, 0) at time (l + m - 1)
                llr3        : out std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (1, 1) at time (l + m - 1)
                a           : out std_logic;                    -- decoded value of a at time (l + m - 1)
                b           : out std_logic                     -- decoded value of b at time (l + m - 1)
                );
    end component;
    
    component extInf
        port    (
                llr0    : in  std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (0, 0)
                llr1    : in  std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (0, 1)
                llr2    : in  std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (1, 0)
                llr3    : in  std_logic_vector(ACC_DIST_WIDTH - 1 downto 0);    -- LLR for (a, b) = (1, 1)
                zin     : in  ARRAY4c;                                          -- extrinsic information input signal
                a       : in  std_logic_vector(SIG_WIDTH - 1 downto 0);         -- decoder systematic input signal
                b       : in  std_logic_vector(SIG_WIDTH - 1 downto 0);         -- decoder systematic input signal
                zout    : out ARRAY4c                                           -- extrinsic information output signal
                );
    end component;
    
    component sova
        port    (
                clk     : in  std_logic;                                -- clock
                rst     : in  std_logic;                                -- negative reset
                aNoisy  : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                bNoisy  : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                yNoisy  : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                wNoisy  : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                zin     : in  ARRAY4c;                                  -- extrinsic information input
                zout    : out ARRAY4c;                                  -- extrinsic information output
                aClean  : out std_logic;                                -- decoded systematic data
                bClean  : out std_logic                                 -- decoded systematic data
                );
    end component;
    
    component zPermut
        generic (
                flip        : integer := 0      -- initialisation (permutation on/off)
                );
        port    (
                flipflop    : in  std_logic;    -- permutation control signal (on/off)
                z           : in  ARRAY4c;      -- original extrinsic information
                zPerm       : out ARRAY4c       -- permuted extrinsic information
                );
    end component;
    
    component interleaver
        generic (
                delay       : integer := 0;     -- number of clock cycles to wait before starting the (de)interleaver
                way         : integer := 0      -- 0 for interleaving, 1 for deinterleaving
                );
        port    (
                clk         : in  std_logic;        -- clock
                rst         : in  std_logic;        -- negative reset
                d           : in  std_logic_vector; -- input data
                q           : out std_logic_vector  -- interleaved data
                );
    end component;
    
    component abPermut
        generic (
                flip        : integer := 0                                  -- initialisation (permutation on/off)
                );
        port    (
                flipflop    : in  std_logic;                                -- permutation control signal (on/off)
                a           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information
                b           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- origiral systematic information
                abPerm      : out ARRAY2a                                   -- permuted systematic information
                );
    end component;
    
    component iteration
        generic (
                delay       : integer := 0                                  -- additional delay created by the previous iterations
                );
        port    (
                clk         : in  std_logic;                                -- clock
                rst         : in  std_logic;                                -- negative reset
                flipflop    : in  std_logic;                                -- permutation control signal (on/off)
                a           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                b           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                y           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                w           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                yInt        : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                wInt        : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- received decoder signal
                zin         : in  ARRAY4c;                                  -- extrinsic information from the previous iteration
                zout        : out ARRAY4c;                                  -- extrinsic information to the next iteration
                aDec        : out std_logic;                                -- decoded signal
                bDec        : out std_logic;                                -- decoded signal
                aDel        : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
                bDel        : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
                yDel        : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
                wDel        : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
                yIntDel     : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- delayed received decoder signal
                wIntDel     : out std_logic_vector(SIG_WIDTH - 1 downto 0)  -- delayed received decoder signal
                );
    end component;
    
    component clkDiv
        port    (
                clk     : in  std_logic;    -- clock
                rst     : in  std_logic;    -- negative reset
                clkout  : out std_logic     -- clock which frequency is half of the input clock
                );
    end component;
    
    component limiter
        port    (
                a       : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                b       : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                y       : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                w       : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                yInt    : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                wInt    : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- decoder input signal
                aLim    : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
                bLim    : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
                yLim    : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
                wLim    : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
                yIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- limited signal
                wIntLim : out std_logic_vector(SIG_WIDTH - 1 downto 0)  -- limited signal
                );
    end component;
    
    component punct
        port    (
                clk         : in  std_logic;                                -- clock
                rst         : in  std_logic;                                -- negative reset
                y           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
                w           : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
                yInt        : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
                wInt        : in  std_logic_vector(SIG_WIDTH - 1 downto 0); -- original data
                yPunct      : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
                wPunct      : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
                yIntPunct   : out std_logic_vector(SIG_WIDTH - 1 downto 0); -- punctured data
                wIntPunct   : out std_logic_vector(SIG_WIDTH - 1 downto 0)  -- punctured data
                );
    end component;
end;