reduction_synth.vhd

来自「turbo码的verilog程序」· VHDL 代码 · 共 58 行

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----                                                              ----
----  reduction_synth.vhd                                         ----
----                                                              ----
----  This file is part of the turbo decoder IP core project      ----
----  http://www.opencores.org/projects/turbocodes/               ----
----                                                              ----
----  Author(s):                                                  ----
----      - David Brochart([e-mail])               ----
----                                                              ----
----  All additional information is available in the README.txt   ----
----  file.                                                       ----
----                                                              ----
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----                                                              ----
---- Copyright (C) 2005 Authors                                   ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more  ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
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architecture synth of reduction is
begin
    process (org)
        variable msb : std_logic;
    begin
        msb := '1';
        for i in 0 to 7 loop
            msb := msb and org(i)(ACC_DIST_WIDTH - 1);
        end loop;
        for i in 0 to 7 loop
            chd(i)(ACC_DIST_WIDTH - 2 downto 0) <= org(i)(ACC_DIST_WIDTH - 2 downto 0);
            chd(i)(ACC_DIST_WIDTH - 1)          <= (not msb) and org(i)(ACC_DIST_WIDTH - 1);
        end loop;
    end process;
end;