sdh_top_testbench.vhd

帧同步检测源码

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity sdh_transact_top_tb is
end sdh_transact_top_tb;

architecture TB_ARCHITECTURE of sdh_transact_top_tb is
	-- Component declaration of the tested unit
	component sdh_transact_top
	port(
		rc_clk : in std_logic;
		reset : in std_logic;
		clk_10m : in std_logic;
		sdh_din : in std_logic_vector(7 downto 0);
		E1_out : out std_logic;
		F1_out : out std_logic;
		clk_64k : out std_logic;
		DDC1_out : out std_logic;
		clk_192k : out std_logic;
		sdh_cost_out : out std_logic;
		sdh_cost_den : out std_logic;
		clk_10m_out : out std_logic );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal rc_clk : std_logic;
	signal reset : std_logic;
	signal clk_10m : std_logic;
	signal sdh_din : std_logic_vector(7 downto 0);
	-- Observed signals - signals mapped to the output ports of tested entity
	signal E1_out : std_logic;
	signal F1_out : std_logic;
	signal clk_64k : std_logic;
	signal DDC1_out : std_logic;
	signal clk_192k : std_logic;
	signal sdh_cost_out : std_logic;
	signal sdh_cost_den : std_logic;
	signal clk_10m_out : std_logic;
	signal cnt : integer range 0 to 2429;  
	signal rand_serial : std_logic_vector(19 downto 0);	 
	signal self_count : std_logic_vector(7 downto 0);  
	signal frame_cnt : integer range 0 to 100;
	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : sdh_transact_top
		port map (
			rc_clk => rc_clk,
			reset => reset,
			clk_10m => clk_10m,
			sdh_din => sdh_din,
			E1_out => E1_out,
			F1_out => F1_out,
			clk_64k => clk_64k,
			DDC1_out => DDC1_out,
			clk_192k => clk_192k,
			sdh_cost_out => sdh_cost_out,
			sdh_cost_den => sdh_cost_den,
			clk_10m_out => clk_10m_out
		);

	-- Add your stimulus here ...		
	clk_19m_sti : process
	begin
		rc_clk <= '0';
		wait for 25.72 ns;
		rc_clk <= '1';
		wait for 25.72 ns;
	end process;
	
	clk_10m_sti : process
	begin
		clk_10m <= '0' ;
		wait for 50 ns;
		clk_10m <= '1';
		wait for 50 ns;
	end process;
	
	reset_sti : process
	begin
		reset <= '0';
		wait for 500 ns;
		reset <= '1';
		wait;
	end process;   
	
	sdh_din_sti : process(rc_clk,reset)
	begin
		if reset='0'then
			sdh_din <= (others => '0');	  
			rand_serial <= "00000000000000000001";	   
			self_count <= (others => '0');	   
			frame_cnt <= 0;
		elsif rising_edge(rc_clk) then		 
			for i in 0 to 18 loop
				rand_serial(i+1) <= rand_serial(i);
			end loop;
			rand_serial(0) <= rand_serial(19) xor rand_serial(0) xor rand_serial(4);
			
			if cnt <= 2 then	
				if frame_cnt=0 or frame_cnt=1 or frame_cnt=10 or frame_cnt=11 then
					sdh_din <= "10110110";
				else
					sdh_din <= "11110110";	  
				end if;
				
				cnt <= cnt+1;
			elsif cnt <= 5 then		  
				if frame_cnt=12 or frame_cnt=14 or frame_cnt=20 then
					sdh_din <= "00111000";
				else
					sdh_din <= "00101000"; 	 
				end if;
				cnt <= cnt+1;		   
			elsif cnt = 273 or cnt=276 or cnt= 540 or cnt=543 or cnt=546 then
				sdh_din <= self_count;		 
				cnt <= cnt+1;
			elsif cnt /= 2429 then
				cnt <= cnt +1;
				sdh_din <= rand_serial(7 downto 0);
			else	
				self_count <= self_count+1;
				frame_cnt <= frame_cnt+1;
				cnt <= 0;
			end if;	
		end if;
	end process;
	

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_sdh_transact_top of sdh_transact_top_tb is
	for TB_ARCHITECTURE
		for UUT : sdh_transact_top
			use entity work.sdh_transact_top(sdh_transact_top);
		end for;
	end for;
end TESTBENCH_FOR_sdh_transact_top;