pe_lad2mem_if_entarch.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

          K_Reg_Read <= '1';
        end if;
      end if;

      --
      --  If any read is performed to the register *or*
      --  DPM portion of this unit, set the K_Read 
      --  status bit
      --
      if ( ( ( LAD_Bus_In.Reg_Strobe_n = '0' ) and
             ( LAD_Bus_In.Write_Sel_n = '1' ) ) and
           ( ( Reg_Base_Addr_Sel = '1' ) or
             ( DPM_Base_Addr_Sel = '1' ) ) ) then
        K_Read <= '1';
      else
        K_Read <= '0';
      end if;

    end if;
  end process;

  ----------------------------------------------------------------------
  --
  --  K-clocked process that is used to implement the DPM/memory
  --  transfer status.  The transfer is said to be "done" when an
  --  acknowledgement is received from the M_Clk-side.  The transfer
  --  is said to be "not done" when a new request is received from
  --  the host.  The done status bit starts off as "not done".
  --
  ----------------------------------------------------------------------
  K_Req_Pulse <= K_Req xor K_Req_d;
  K_Ack_Pulse <= K_Ack_dd xor K_Ack_ddd;

  K_Status : process ( Global_Reset, K_CLK )
  begin
    if ( Global_Reset = '1' ) then

      K_Req_d <= '0';

      K_Ack <= '0';
      K_Ack_d <= '0';
      K_Ack_dd <= '0';
      K_Ack_ddd <= '0';

      K_Done <= '0';

    elsif ( rising_edge ( K_CLK ) ) then

      K_Req_d <= K_Req;

      --
      --  NOTE: Three levels of registers are used
      --  to handle multi-clock meta-stability 
      --  design issues.
      --
      K_Ack <= M_Ack;
      K_Ack_d <= K_Ack;
      K_Ack_dd <= K_Ack_d;
      K_Ack_ddd <= K_Ack_dd;

      if ( K_Req_Pulse = '1' ) then
        K_Done <= '0';
      elsif ( K_Ack_Pulse = '1' ) then
        K_Done <= '1';
      end if;

    end if;
  end process;



  --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  --
  --  M-clock side logic
  --
  --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

  M_Req_Pulse <= M_Req_dd xor M_Req_ddd;

  ----------------------------------------------------------------------
  --
  --  M-clocked process that handles the control of the DPM and memory
  --  interfaces.
  --
  ----------------------------------------------------------------------
  M_CLK <= Clocks_In.M_Clk;
  M_Control : process ( Global_Reset, M_CLK )
  begin
    if ( Global_Reset = '1' ) then

      M_Ack <= '0';

      M_Busy <= '0';
      M_Count <= ( others => '0' );

      M_DPM_CE <= '0';
      M_DPM_Offset <= ( others => '0' );

      M_Mem_Write_Sel_n <= '1';
      M_Mem_Strobe_n <= '1';
      M_Mem_Addr <= ( others => '0' );

    elsif ( rising_edge ( M_CLK ) ) then

      --
      --  Acknowledge the DPM/memory access when
      --  the M-clock side becomes "not busy"
      --
      if ( ( M_Busy_d = '0' ) and
           ( M_Busy_dd = '1' ) ) then
        M_Ack <= not M_Ack;
      end if;

      --
      --  If a request is received from the K-clocked
      --  side, load the DPM/memory control registers
      --
      if ( M_Req_Pulse = '1' ) then

        M_Busy <= '0';
        M_Count <= K_Count;

        M_DPM_CE <= '0';
        M_DPM_Offset <= K_DPM_Offset;

        M_Mem_Write_Sel_n <= K_Mem_Write_Sel_n;
        M_Mem_Strobe_n <= '1';
        M_Mem_Addr <= K_Mem_Addr;

      else

        --
        --  If the DWORD count is non-zero,
        --  then the control interface is said
        --  to be "busy", otherwise it is "not
        --  busy"
        --
        if ( M_Count /= "000000000" ) then
          M_Count <= M_Count - 1;
          M_Busy <= '1';
        else
          M_Busy <= '0';
        end if;

        --
        --  In the case of a memory write access,
        --  the data is first read out of the DPM,
        --  then it is written to the memory.
        --
        if ( M_Mem_Write_Sel_n = '0' ) then

          M_DPM_CE <= M_Busy;

          if ( M_Busy_d = '1' ) then
            M_DPM_Offset <= M_DPM_Offset + 1;
          end if;

          M_Mem_Strobe_n <= not M_Busy_d;

          if ( M_Busy_dd = '1' ) then
            M_Mem_Addr <= M_Mem_Addr + 1;
          end if;

        --
        --  In the case of a memory read access,
        --  the data is first read out of the 
        --  memory, then it is written to the DPM
        --  as it becomes available from the
        --  memory interface pipeline.
        --
        elsif ( M_Mem_Write_Sel_n = '1' ) then

          M_Mem_Strobe_n <= not M_Busy;

          if ( M_Busy_d = '1' ) then
            M_Mem_Addr <= M_Mem_Addr + 1;
          end if;

          M_DPM_CE <= not Mem_Data_Valid_n;

          if ( M_Mem_Data_Valid_n = '0' ) then
            M_DPM_Offset <= M_DPM_Offset + 1;
          end if;

        end if;

      end if;

    end if;
  end process;

  ----------------------------------------------------------------------
  --
  --  M-clocked process that handles the implementation of the
  --  necessary delay registers needed by the control interface.
  --
  ----------------------------------------------------------------------
  M_Delay : process ( Global_Reset, M_CLK )
  begin
    if ( Global_Reset = '1' ) then

      M_Req <= '0';
      M_Req_d <= '0';
      M_Req_dd <= '0';
      M_Req_ddd <= '0';

      M_Busy_d <= '0';
      M_Busy_dd <= '0';

      M_Mem_Data_In <= ( others => '0' );
      M_Mem_Data_Valid_n <= '1';

      Mem_Addr <= (  Mem_Addr'range => '0' );
      Mem_Data_Out <= ( others => '0' );
      Mem_Strobe_n <= '1';
      Mem_Write_Sel_n <= '1';

    elsif ( rising_edge ( M_CLK ) ) then

      --
      --  NOTE: Three levels of registers are used
      --  to handle multi-clock meta-stability 
      --  design issues.
      --
      M_Req <= K_Req;
      M_Req_d <= M_Req;
      M_Req_dd <= M_Req_d;
      M_Req_ddd <= M_Req_dd;

      M_Busy_d <= M_Busy;
      M_Busy_dd <= M_Busy_d;

      M_Mem_Data_In <= Mem_Data_In;
      M_Mem_Data_Valid_n <= Mem_Data_Valid_n;

      Mem_Addr <= M_Mem_Addr;
      Mem_Data_Out <= M_DPM_Data_Out;
      Mem_Strobe_n <= M_Mem_Strobe_n;
      Mem_Write_Sel_n <= M_Mem_Write_Sel_n;

    end if;
  end process;


  --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  --
  --  Dual-ported block RAM : Used to buffer incoming and outgoing data
  --
  --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  K_DPM_Addr <= LAD_Bus_In.Addr(7 downto 0);
  K_DPM_Data_In <= LAD_Bus_In.Data_In;
  K_DPM_WE <= not LAD_Bus_In.Write_Sel_n;
  K_DPM_CE <= ( not LAD_Bus_In.Reg_Strobe_n ) and DPM_Base_Addr_Sel;

  M_DPM_Addr <= M_DPM_Offset;
  M_DPM_Data_In <= M_Mem_Data_In;
  M_DPM_WE <= not M_Mem_Data_Valid_n;

  U_RAMB : RAMB_256x32_DP
    port map
    (
      addra => K_DPM_Addr,
      addrb => M_DPM_Addr,
      dia   => K_DPM_Data_In,
      dib   => M_DPM_Data_In,
      clka  => K_CLK,
      clkb  => M_CLK,
      wea   => K_DPM_WE,
      web   => M_DPM_WE,
      ena   => K_DPM_CE,
      enb   => M_DPM_CE,
      rsta  => Global_Reset,
      rstb  => Global_Reset,
      doa   => K_DPM_Data_Out,
      dob   => M_DPM_Data_Out
    );

end Standard_256;