pe_lad2mem_if_entarch.vhd

arm9_fpga2_verilog是一个可以综合的用verilog写的arm9的ip软核

------------------------------------------------------------------------
--
--  Copyright (C) 1998-1999, Annapolis Micro Systems, Inc.
--  All Rights Reserved.
--
------------------------------------------------------------------------

------------------------------------------------------------------------
--
--  Entity        : LAD_To_Mem_Std_IF
--
--  Architecture  : Standard_256
--
--  Filename      : pe_lad2mem_if_entarch.vhd
--
--  Date          : 6/23/99
--
--  Description   : Models a pre-fetch/store buffer that when accessed
--                  from the LAD bus will perform memory access. During
--                  a write to memory, the data is read from the DPM 
--                  buffer and written to memory.  During a read from 
--                  memory, the data is read from the memory and written
--                  to the DPM buffer.  The host then reads from the
--                  DPM buffer.
--
------------------------------------------------------------------------

------------------------------- Glossary -------------------------------
--
--  Name Key:
--  =========
--  _AS       : Address Strobe
--  _CE       : Clock Enable
--  _CS       : Chip Select
--  _DS       : Data Strobe
--  _EN       : Enable
--  _OE       : Output Enable
--  _RD       : Read Select
--  _WE       : Write Enable
--  _WR       : Write Select
--  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
--              level of delay)
--  _n        : Active low signals (must be last part of name)
--
--  Generic Name          Description
--  ====================  ==============================================
--  LAD_ADDR_BASE         LAD bus address base used to select device
--  LAD_ADDR_MASK         LAD bus address mask used to select device
--
--  Port Name             Width   Dir   Description
--  ====================  =====   ===   ================================
--  Global_Reset            1      I    Global reset signal
--  Clocks_In.M_Clk         1      I    Memory clock
--  Clocks_In.P_Clk         1      I    Processor clock
--  Clocks_In.K_Clk         1      I    LAD-bus clock
--  Clocks_In.U_Clk         1      I    User clock
--  Clocks_In.M_Clk_Locked  1      I    M_Clk CLKDLL locked flag
--  Clocks_In.P_Clk_Locked  1      I    P_Clk CLKDLL locked flag
--  Clocks_In.K_Clk_Locked  1      I    K_Clk CLKDLL locked flag
--  Clocks_In.U_Clk_Locked  1      I    U_Clk CLKDLL locked flag
--  LAD_Bus_In.Addr        23      I    LAD bus address bus input
--  LAD_Bus_In.Data_In     32      I    LAD bus data bus input
--  LAD_Bus_In.Reg_Strobe_n 1      I    LAD bus register access strobe
--  LAD_Bus_In.Mem_Strobe_n 1      I    LAD bus memory access strobe
--  LAD_Bus_In.Write_Sel_n  1      I    LAD bus write select
--  LAD_Bus_In.DMA_Chan     2      I    LAD bus DMA channel number
--  LAD_Bus_Out.Data_Out   32      O    LAD bus data bus output
--  LAD_Bus_In.Int_Req_n    1      O    LAD bus interrupt request
--  LAD_Bus_Out.DMA_Stat    2      O    LAD bus DMA channel status flags
--  LAD_Data_OE_n           1      O    LAD bus data bus output enable
--  Mem_Data_In            32      I    Memory input data bus
--  Mem_Data_Valid_n        1      I    Memory data input valid flag
--  Mem_Addr               20      O    Memory address bus
--  Mem_Data_Out           32      O    Memory output data bus
--  Mem_Strobe_n            1      O    Memory access strobe
--  Mem_Write_Sel_n         1      O    Memory write select
--
------------------------------------------------------------------------

-------------------------- Library Declarations ------------------------

library IEEE, SYSTEM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use WORK.PE_Package.all;
use SYSTEM.Xilinx_Package.all;

--------------------------- Entity Declaration -------------------------

entity LAD_To_Mem_Std_IF is
  port
  (
    Global_Reset      : in    std_logic;
    Clocks_In         : in    Clock_Std_IF_In_Type;
    LAD_Bus_In        : in    LAD_Bus_Std_IF_In_Type;
    LAD_Bus_Out       :   out LAD_Bus_Std_IF_Out_Type;
    LAD_Bus_OE_n      :   out std_logic;
    Mem_Data_In       : in    std_logic_vector(31 downto 0);
    Mem_Data_Valid_n  : in    std_logic;
    Mem_Addr          :   out std_logic_vector (19 downto 0);
    Mem_Data_Out      :   out std_logic_vector(31 downto 0);
    Mem_Strobe_n      :   out std_logic;
    Mem_Write_Sel_n   :   out std_logic
  );
  constant ADDR_MASK : std_logic_vector (11 downto 8) := x"F";
  constant DPM_ADDR_BASE : std_logic_vector (11 downto 8) := x"1";
  constant REG_ADDR_BASE : std_logic_vector (11 downto 8) := x"0";
end LAD_To_Mem_Std_IF;

------------------------ Architecture Declaration ----------------------

architecture Standard_256 of LAD_To_Mem_Std_IF is

  ------------------------------- Glossary -----------------------------
  --
  --  Name Key:
  --  =========
  --  _AS       : Address Strobe
  --  _CB       : CardBus
  --  _CE       : Clock Enable
  --  _CS       : Chip Select
  --  _DS       : Data Strobe
  --  _EN       : Enable
  --  _OE       : Output Enable
  --  _PE       : Processing Element
  --  _RD       : Read Select
  --  _WE       : Write Enable
  --  _WR       : Write Select
  --  _d[d...]  : Delayed (registered) signal (each 'd' denotes one 
  --              level of delay)
  --  _n        : Active low signals (must be last part of name)
  --
  --  Name                          Description
  --  =========================     ======================================
  --
  ----------------------------------------------------------------------

  signal Reg_Base_Addr_Sel : std_logic;
  signal DPM_Base_Addr_Sel : std_logic;

  signal K_Req : std_logic;
  signal K_Req_d : std_logic;
  signal K_Req_Pulse : std_logic;
  signal K_DPM_Offset : std_logic_vector(7 downto 0);
  signal K_Mem_Addr : std_logic_vector(19 downto 0);
  signal K_Mem_Write_Sel_n : std_logic;
  signal K_Count : std_logic_vector(8 downto 0);
  signal K_Reg_Read : std_logic;
  signal K_Read : std_logic;
  signal K_Done : std_logic;
  signal K_Ack : std_logic;
  signal K_Ack_d : std_logic;
  signal K_Ack_dd : std_logic;
  signal K_Ack_ddd : std_logic;
  signal K_Ack_Pulse : std_logic;
  signal K_DPM_Addr : std_logic_vector(7 downto 0);
  signal K_DPM_Data_In : std_logic_vector(31 downto 0);
  signal K_DPM_Data_Out : std_logic_vector(31 downto 0);
  signal K_DPM_WE : std_logic;
  signal K_DPM_CE : std_logic;
  signal K_CLK : std_logic;

  signal M_Req : std_logic;
  signal M_Req_d : std_logic;
  signal M_Req_dd : std_logic;
  signal M_Req_ddd : std_logic;
  signal M_Req_Pulse : std_logic;
  signal M_DPM_Offset : std_logic_vector(7 downto 0);
  signal M_Count : std_logic_vector(8 downto 0);
  signal M_Ack : std_logic;
  signal M_Busy : std_logic;
  signal M_Busy_d : std_logic;
  signal M_Busy_dd : std_logic;
  signal M_DPM_Addr : std_logic_vector(7 downto 0);
  signal M_DPM_Data_In : std_logic_vector(31 downto 0);
  signal M_DPM_Data_Out : std_logic_vector(31 downto 0);
  signal M_DPM_WE : std_logic;
  signal M_DPM_CE : std_logic;
  signal M_Mem_Data_In : std_logic_vector(31 downto 0);
  signal M_Mem_Data_Valid_n : std_logic;
  signal M_Mem_Addr : std_logic_vector(19 downto 0);
  signal M_Mem_Strobe_n : std_logic;
  signal M_Mem_Write_Sel_n : std_logic;
  signal M_CLK : std_logic;

begin
  -- Covert the Generics back to std_logic_vectors
  


  --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
  --
  --  K-clock side logic
  --
  --@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

  ----------------------------------------------------------------------
  --
  --  LAD bus output signals
  --
  ----------------------------------------------------------------------
  LAD_Bus_Out.Data_Out <= 
    (0 => K_Done, others => '0') when ( K_Reg_Read = '1' )
    else K_DPM_Data_Out;

  LAD_Bus_Out.Int_Req_n <= '1';

  LAD_Bus_Out.DMA_Stat <= ( others => '0' );

  LAD_Bus_OE_n <= not K_Read;

  ----------------------------------------------------------------------
  --
  --  Decode the incoming LAD bus address to see if we are being 
  --  selected; drive the outgoing LAD data from the M_Clk-side
  --  status registers, otherwise use the block RAM output.
  --
  ----------------------------------------------------------------------

  Reg_Base_Addr_Sel <= '1' when ( ( LAD_Bus_In.Addr(ADDR_MASK'range) and 
                                    ADDR_MASK ) = REG_ADDR_BASE ) else '0';

  DPM_Base_Addr_Sel <= '1' when ( ( LAD_Bus_In.Addr(ADDR_MASK'range) and 
                                    ADDR_MASK ) = DPM_ADDR_BASE ) else '0';

  ----------------------------------------------------------------------
  --
  --  K-clocked process that is used to implement the LAD registers
  --  that are a part of this design.  The registers in this design
  --  are as follows:
  --
  --      Addr  Description
  --      ----  ------------------------------------------------------
  --        0   Contains starting dual-port memory (DPM) offset and
  --            memory address
  --        1   Contains read/write control bit and DWORD count
  --        2   Reserved
  --        3   "Start" bit control register: any write to this address
  --            will initiate a DPM/memory transfer
  --
  ----------------------------------------------------------------------
  K_CLK <= Clocks_In.K_Clk;
  K_LAD_Regs : process ( Global_Reset, K_CLK )
  begin
    if ( Global_Reset = '1' ) then

      K_DPM_Offset <= ( others => '0' );
      K_Mem_Addr <= ( others => '0' );
      K_Mem_Write_Sel_n <= '1';
      K_Count <= ( others => '0' );
      K_Req <= '0';

      K_Reg_Read <= '0';
      K_Read <= '0';

    elsif ( rising_edge ( K_CLK ) ) then

      K_Reg_Read <= '0';

      if ( ( LAD_Bus_In.Reg_Strobe_n = '0' ) and
           ( Reg_Base_Addr_Sel = '1' ) ) then
        if ( LAD_Bus_In.Write_Sel_n = '0' ) then
          case LAD_Bus_In.Addr(1 downto 0) is
            when "00" =>
              K_DPM_Offset <= LAD_Bus_In.Data_In(30 downto 23);
              K_Mem_Addr <= LAD_Bus_In.Data_In(19 downto 0);
            when "01" =>
              K_Mem_Write_Sel_n <= LAD_Bus_In.Data_In(20);
              K_Count <= LAD_Bus_In.Data_In(8 downto 0);
            when "11" =>
              K_Req <= not K_Req;
            when others =>
              NULL;
          end case;
        --
        --  If any read is performed to this register
        --  portion of this unit, set the K_Reg_Read
        --  status bit
        --
        elsif ( LAD_Bus_In.Write_Sel_n = '1' ) then