d_out_usb.vhd

VHDL编译,本程序是从USB GPIF口SRAM传输数据,且形成乒乓结构传输

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity d_out is
    Port ( clk : in std_logic;

--USB GPIF INTERFACE
           USB_XCLK : in std_logic;
           USB_RDY : out std_logic_vector(5 downto 0);
           USB_CTRL : in std_logic_vector(5 downto 0);
           USB_XDATA : inout std_logic_vector(15 downto 0);
--USB OTHER
           USB_PC0 : in std_logic;
           USB_PC1 : in std_logic;
           USB_PC2 : in std_logic;
           USB_PC3: in std_logic;
           USB_PC4 : out std_logic;
           USB_PC5 : out std_logic;
           USB_PC6 : out std_logic;
           USB_PC7 : out std_logic;

--SRAM INTERFACE
           SRAM_CS1 : out std_logic;
           SRAM_OE1 : out std_logic;
           SRAM_WE1 : out std_logic;
           SRAM_ADDR1 : out std_logic_vector(17 downto 0);
           SRAM_Data1 : inout std_logic_vector(15 downto 0);
           SRAM_CS2 : out std_logic;
           SRAM_OE2 : out std_logic;
           SRAM_WE2 : out std_logic;
           SRAM_ADDR2 : out std_logic_vector(17 downto 0);
           SRAM_Data2 : inout std_logic_vector(15 downto 0);
		  
--OUTPUT 
           OUT_DATA : out std_logic;
           OUT_FLAG : out std_logic;
           OUT_CLKA : out std_logic;
           OUT_CLKB : out std_logic;
           OUT_D : out std_logic_vector(15 downto 0);
		   LED1 : out std_logic;
		   LED2 : out std_logic
		);
end d_out;

architecture d_out_arch of d_out is

--control signal
signal reset,DO_RUN,WR_FLAG,DO_WORK:std_logic;
signal clk_div:std_logic_vector(3 downto 0);

--SRAM interface
signal SRAM_RD_CLK,SRAM_WR_CLK:std_logic;
signal SRAM_ADDR_RD:std_logic_vector(18 downto 0);
signal SRAM_ADDR_WR:std_logic_vector(18 downto 0);
signal CHANNEL_SEL,MEMORY_OK:std_logic;		

--WORK CONTROL STATE MACHINE				 
type WORK_states is(WORK_idle,WORK_WRITE_EN,WORK_RW_STATE,WORK_RW_WRITE2,WORK_RW_WAIT2,WORK_RW_WRITE1,WORK_RW_WAIT1);
signal WORK_CURRENT_STATE,WORK_NEXT_STATE: WORK_states;
signal WR_EN,sWR_EN:std_logic;
signal RD_EN,sRD_EN:std_logic;		

-----------------------------------------------------------------------------------------------------
begin
reset <= USB_PC0; --Soft reset
DO_RUN <=USB_PC1; --RUN/STOP
--USB_XCLK <=CLK;
OUT_CLKA <= clk_div(0);
process(clk)
begin
	if(clk'event and clk='1')then clk_div <= clk_div+1;
	end if;
end process;

process(DO_WORK,WR_EN)
begin
	if(DO_WORK = '0') then WR_FLAG <='0';
	elsif(WR_EN'event and WR_EN='1')then WR_FLAG <= NOT WR_FLAG;
	end if;
end process;

--****************************************************************************************************
--************************************    SRAM INTERFACE    ****************************************
--****************************************************************************************************
SRAM_CS1 <= not DO_WORK;
SRAM_CS2 <= not DO_WORK;
SRAM_WR_CLK <= USB_CTRL(0);-- OR USB_XCLK;
SRAM_RD_CLK <=clk_div(0);

--SRAM address generator
SRAM_ADDR_RD_GEN:process(RD_EN,SRAM_RD_CLK)
begin
	if(RD_EN ='0') then SRAM_ADDR_RD <=(others =>'0');
	elsif(SRAM_RD_CLK'event and SRAM_RD_CLK='1')then 
		SRAM_ADDR_RD<=SRAM_ADDR_RD +1;  --SRAM ADDRESS 
	end if;
end process SRAM_ADDR_RD_GEN;
CHANNEL_SEL<=SRAM_ADDR_RD(18);

SRAM_ADDR_WR_GEN:process(WR_EN,SRAM_WR_CLK)
begin
	if(WR_EN ='0') then SRAM_ADDR_WR <=(others =>'0');
	elsif(SRAM_WR_CLK'event and SRAM_WR_CLK='1')then 
		SRAM_ADDR_WR<=SRAM_ADDR_WR +1;  --SRAM ADDRESS 
	end if;
end process SRAM_ADDR_WR_GEN;
MEMORY_OK<=SRAM_ADDR_WR(18);

SRAM_ADDR1<=SRAM_ADDR_RD(17 DOWNTO 0)WHEN(CHANNEL_SEL='0') ELSE			--READ SRAM1
			SRAM_ADDR_WR(17 DOWNTO 0);
SRAM_ADDR2<=SRAM_ADDR_RD(17 DOWNTO 0)WHEN(CHANNEL_SEL='1') ELSE
			SRAM_ADDR_WR(17 DOWNTO 0);
SRAM_OE1 <= SRAM_RD_CLK WHEN(CHANNEL_SEL='0' and RD_EN ='1') ELSE '1'; --READ SRAM1
SRAM_OE2 <= SRAM_RD_CLK WHEN(CHANNEL_SEL='1' and RD_EN ='1') ELSE '1'; --READ SRAM2
SRAM_WE1 <= SRAM_WR_CLK WHEN(WR_FLAG ='1' and DO_WORK='1') ELSE '1'; --READ SRAM2(SRAM1 ENABLE WRITE)
SRAM_WE2 <= SRAM_WR_CLK WHEN(WR_FLAG ='0' and DO_WORK='1') ELSE '1'; --READ SRAM1(SRAM2 ENABLE WRITE)
SRAM_Data1 <=USB_XDATA WHEN(CHANNEL_SEL='1') ELSE "ZZZZZZZZZZZZZZZZ";
SRAM_Data2 <=USB_XDATA WHEN(CHANNEL_SEL='0') ELSE "ZZZZZZZZZZZZZZZZ";
OUT_D <= SRAM_Data1 WHEN(CHANNEL_SEL='0') ELSE SRAM_Data2;
--****************************************************************************************************
--************************************    FSM CONTROL    **********************************************
--****************************************************************************************************
USB_RDY(0)<=WR_EN;
--LED1<= WR_EN;
--switch State
WORK_Switch_state:process(reset,clk,WORK_NEXT_STATE)
begin
	if(reset = '0')then
		WR_EN<='0';
		RD_EN<='0';
		WORK_CURRENT_STATE <= WORK_idle;
	elsif(clk'event and clk = '1')then
		WR_EN<=sWR_EN;
		RD_EN<=sRD_EN;
		WORK_CURRENT_STATE <= WORK_NEXT_STATE;
	end if;
end process WORK_Switch_state;

--Change state
WORK_Change_state:process(WORK_CURRENT_STATE,DO_RUN,MEMORY_OK,CHANNEL_SEL)
begin
	DO_WORK<='1';
	sWR_EN<='0';
	sRD_EN<='1';
	LED2<='1';
	LED1<='0';
	case WORK_CURRENT_STATE is
		when WORK_idle	=>	DO_WORK<='0';sRD_EN<='0';LED2<='0';
							if(DO_RUN ='1') then WORK_NEXT_STATE	<= WORK_WRITE_EN;
							else WORK_NEXT_STATE	<= WORK_idle;
							end if;

		when WORK_WRITE_EN	=>	sWR_EN<='1';sRD_EN<='0';
							if(MEMORY_OK = '1') then WORK_NEXT_STATE	<= WORK_RW_STATE;
							else WORK_NEXT_STATE	<= WORK_WRITE_EN;
							end if;

		when WORK_RW_STATE	=> WORK_NEXT_STATE	<= WORK_RW_WRITE2;
		
		when WORK_RW_WRITE2=> sWR_EN<='1';
							if(CHANNEL_SEL='1' ) then LED1<='1';
							end if;
							if(MEMORY_OK ='1') then WORK_NEXT_STATE	<= WORK_RW_WAIT2;
							else WORK_NEXT_STATE	<= WORK_RW_WRITE2;
							end if;
							
		when WORK_RW_WAIT2=>if(CHANNEL_SEL='1' ) then
								if(DO_RUN='0') then WORK_NEXT_STATE	<= WORK_idle;
								else WORK_NEXT_STATE	<= WORK_RW_WRITE1;
								end if;
							else WORK_NEXT_STATE <= WORK_RW_WAIT2;
							end if;
		when WORK_RW_WRITE1=> sWR_EN<='1';
							if(CHANNEL_SEL='0' ) then LED1<='1';
							end if;
							if(MEMORY_OK ='1') then WORK_NEXT_STATE	<= WORK_RW_WAIT1;
							else WORK_NEXT_STATE	<= WORK_RW_WRITE1;
							end if;
							
		when WORK_RW_WAIT1=>if(CHANNEL_SEL='0' ) then
								if(DO_RUN='0') then WORK_NEXT_STATE	<= WORK_idle;
								else WORK_NEXT_STATE	<= WORK_RW_WRITE2;
								end if;
							else WORK_NEXT_STATE <= WORK_RW_WAIT1;
							end if;

		when others	=> DO_WORK<='0';sRD_EN<='0';LED2<='0';WORK_NEXT_STATE	<= WORK_idle;
	end case;
end process WORK_Change_state;

end d_out_arch;