jzsc.vhd

来自「基于vhdl的键盘输入,学校的作业」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jzsc is
	port
		(hiB,hiA:in std_logic;
		 low:in std_logic_vector(1 downto 0);
		 q_BCD:buffer std_logic_vector(3 downto 0);
		 en:in std_logic
		);
end jzsc;

architecture behave of jzsc is
	begin
		process(en)
			begin
				if en='1' then q_BCD(3)<=hiB;
							   q_BCD(2)<=hiA;
							   q_BCD(1)<=low(1);
							   q_BCD(0)<=low(0);
					else q_BCD<=q_BCD;
				end if;
		end process;
end behave;