📄 kb.rpt
字号:
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 07 OR2 4 0 0 4 |B42:11|:51
- 8 - A 02 DFFE 0 2 1 0 |JZSC:14|:5
- 3 - A 02 DFFE 0 2 1 0 |JZSC:14|:7
- 1 - A 07 DFFE 4 1 1 0 |JZSC:14|:9
- 3 - A 07 DFFE 4 1 1 0 |JZSC:14|:11
- 5 - A 02 OR2 0 2 1 0 |74139:2|Y10N (|74139:2|:33)
- 7 - A 02 OR2 0 2 1 0 |74139:2|Y11N (|74139:2|:34)
- 1 - A 02 OR2 0 2 1 0 |74139:2|Y12N (|74139:2|:35)
- 2 - A 02 OR2 0 2 1 0 |74139:2|Y13N (|74139:2|:36)
- 4 - A 02 DFFE + 0 0 0 6 |74161:1|f74161:sub|QA (|74161:1|f74161:sub|:9)
- 6 - A 02 DFFE + 0 1 0 5 |74161:1|f74161:sub|QB (|74161:1|f74161:sub|:87)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: h:\maxplus\c1\kb.rpt
kb
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 2/ 48( 4%) 0/ 48( 0%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\maxplus\c1\kb.rpt
kb
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 4 |B42:11|:51
INPUT 2 clk
Device-Specific Information: h:\maxplus\c1\kb.rpt
kb
** EQUATIONS **
clk : INPUT;
V0 : INPUT;
V1 : INPUT;
V2 : INPUT;
V3 : INPUT;
-- Node name is 'H0'
-- Equation name is 'H0', type is output
H0 = _LC5_A2;
-- Node name is 'H1'
-- Equation name is 'H1', type is output
H1 = _LC7_A2;
-- Node name is 'H2'
-- Equation name is 'H2', type is output
H2 = _LC1_A2;
-- Node name is 'H3'
-- Equation name is 'H3', type is output
H3 = _LC2_A2;
-- Node name is 'Q_BCD0'
-- Equation name is 'Q_BCD0', type is output
Q_BCD0 = _LC3_A7;
-- Node name is 'Q_BCD1'
-- Equation name is 'Q_BCD1', type is output
Q_BCD1 = _LC1_A7;
-- Node name is 'Q_BCD2'
-- Equation name is 'Q_BCD2', type is output
Q_BCD2 = _LC3_A2;
-- Node name is 'Q_BCD3'
-- Equation name is 'Q_BCD3', type is output
Q_BCD3 = _LC8_A2;
-- Node name is '|B42:11|:51'
-- Equation name is '_LC2_A7', type is buried
_LC2_A7 = LCELL( _EQ001);
_EQ001 = !V2
# !V3
# !V0
# !V1;
-- Node name is '|JZSC:14|:5'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = DFFE( _LC6_A2, _LC2_A7, VCC, VCC, VCC);
-- Node name is '|JZSC:14|:7'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = DFFE( _LC4_A2, _LC2_A7, VCC, VCC, VCC);
-- Node name is '|JZSC:14|:9'
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = DFFE( _EQ002, _LC2_A7, VCC, VCC, VCC);
_EQ002 = V0 & V1 & !V2
# V0 & V1 & !V3;
-- Node name is '|JZSC:14|:11'
-- Equation name is '_LC3_A7', type is buried
_LC3_A7 = DFFE( _EQ003, _LC2_A7, VCC, VCC, VCC);
_EQ003 = V0 & V2 & !V3
# V0 & !V1;
-- Node name is '|74139:2|:33' = '|74139:2|Y10N'
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = LCELL( _EQ004);
_EQ004 = _LC6_A2
# _LC4_A2;
-- Node name is '|74139:2|:34' = '|74139:2|Y11N'
-- Equation name is '_LC7_A2', type is buried
_LC7_A2 = LCELL( _EQ005);
_EQ005 = _LC6_A2
# !_LC4_A2;
-- Node name is '|74139:2|:35' = '|74139:2|Y12N'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ006);
_EQ006 = !_LC6_A2
# _LC4_A2;
-- Node name is '|74139:2|:36' = '|74139:2|Y13N'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ007);
_EQ007 = !_LC6_A2
# !_LC4_A2;
-- Node name is '|74161:1|f74161:sub|:9' = '|74161:1|f74161:sub|QA'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = DFFE(!_LC4_A2, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|74161:1|f74161:sub|:87' = '|74161:1|f74161:sub|QB'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC4_A2 & _LC6_A2
# _LC4_A2 & !_LC6_A2;
Project Information h:\maxplus\c1\kb.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,686K
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