b42.vhd

来自「基于vhdl的键盘输入,学校的作业」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity b42 is
	port
		(V:in std_logic_vector(3 downto 0);
		 q42:out std_logic_vector(1 downto 0);
		 check:out std_logic
		);
end b42;

architecture behave of b42 is
	begin
		check<='1' when V(0)='0' else
		       '1' when V(1)='0' else
			   '1' when V(2)='0' else
			   '1' when V(3)='0' else
			   '0';
		q42<="00" when V(0)='0' else
			 "01" when V(1)='0' else
			 "10" when V(2)='0' else
		 	 "11" when V(3)='0' else
			 "00";
end behave;