📄 zuosr8.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity zuosr8 is
port (clk,din,reset:in std_logic;
q:inout std_logic_vector(0 to 7)
p:inout std_logic_vector(0 to 7)
);
end zuosr8;
architecture sr8_arch of zuosr8 is
begin
process(clk,reset,q,p)
begin
if reset='0' then
q<="00000000"; p<="00000000";
elsif clk'event and clk='1' then
q<=q(1 to 7)&din; p<=p(1 to 7)&din;
end if;
end process;
end sr8_arch;
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